[PATCH] D157984: [llvm][ARM][Neon][big-endian] Fix incorrect indexing of lanes

[Oliver Stannard via Phabricator via llvm-commits]

olista01 requested changes to this revision.
olista01 added a comment.
This revision now requires changes to proceed.

I don't think this is the right way to fix this. Endianness shouldn't affect the ordering of lanes in registers, only when they are stored to memory. We've got some documentation on this at https://llvm.org/docs/BigEndianNEON.html.

If this is the right place to fix this, this patch only changes DSubReg_i32_reg, why do the rest not need to be modified too?


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D157984