[PATCH] D157113: [AArch64] Support more types for ZEXT/SEXT with Global Isel

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:5982
+      Register MidRegister = MRI.createGenericVirtualRegister(MidTy);
+      MIRBuilder.buildInstr(MI.getOpcode(), {MidRegister}, {Src});
+      // Unmerge the vector
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Can reduce the indenting now.


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Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:522
+      .lowerIf([=](const LegalityQuery &Query) {
+        return (Query.Types[0].getScalarSizeInBits() >
+                Query.Types[1].getScalarSizeInBits() * 2) &&
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Can you add a comment here explaining that this is trying to convert larger extends into two smaller ones.


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Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:524
+                Query.Types[1].getScalarSizeInBits() * 2) &&
+               (Query.Types[0].isVector()) && 
+               (Query.Types[1].getScalarSizeInBits() == 8 ||
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`(Query.Types[0].isVector())` -> `Query.Types[0].isVector()`


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Comment at: llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir:144
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32)
-    ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
+    ; CHECK-NEXT: %ext:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32)
+    ; CHECK-NEXT: $d0 = COPY %ext(<2 x s32>)
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Is this with update_mir_test_checks? Maybe just replace %ext with %3 in the code below.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D157113/new/

https://reviews.llvm.org/D157113