[llvm] fdbc944 - Fix typos in comments

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-08-15T13:57:21+01:00
New Revision: fdbc944385748e77346c005177ac440d5641d324

URL: https://github.com/llvm/llvm-project/commit/fdbc944385748e77346c005177ac440d5641d324
DIFF: https://github.com/llvm/llvm-project/commit/fdbc944385748e77346c005177ac440d5641d324.diff

LOG: Fix typos in comments

Added: 
    

Modified: 
    llvm/lib/CodeGen/VirtRegMap.cpp
    llvm/lib/Target/ARM/ARMISelLowering.cpp
    llvm/test/CodeGen/X86/AMX/amx-fastpreconfig.mir
    llvm/unittests/ProfileData/MemProfTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index a816bd5b52decc..c1c6ce227334a4 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -311,7 +311,7 @@ void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
   }
 
   // Check all mbb start positions between First and Last while
-  // simulatenously advancing an iterator for each subrange.
+  // simultaneously advancing an iterator for each subrange.
   for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
        MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
     SlotIndex MBBBegin = MBBI->first;

diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 5cb1f434d30e3c..cd220239e9d03a 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -12004,7 +12004,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     TpLoopBody->moveAfter(TpEntry);
     TpExit->moveAfter(TpLoopBody);
 
-    // Finally, remove the memcpy Psuedo Instruction
+    // Finally, remove the memcpy Pseudo Instruction
     MI.eraseFromParent();
 
     // Return the exit block as it may contain other instructions requiring a

diff  --git a/llvm/test/CodeGen/X86/AMX/amx-fastpreconfig.mir b/llvm/test/CodeGen/X86/AMX/amx-fastpreconfig.mir
index 8807cc029ccd70..dcc8d542c70704 100644
--- a/llvm/test/CodeGen/X86/AMX/amx-fastpreconfig.mir
+++ b/llvm/test/CodeGen/X86/AMX/amx-fastpreconfig.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=x86_64-- -mattr=+amx-int8,avx512f -run-pass=fastpretileconfig -o - %s | FileCheck %s
 
-# Test the case which has TILELOADD being mixed in psuedo AMX instruction
+# Test the case which has TILELOADD being mixed in pseudo AMX instruction
 ...
 ---
 name:            main

diff  --git a/llvm/unittests/ProfileData/MemProfTest.cpp b/llvm/unittests/ProfileData/MemProfTest.cpp
index 9d79385ad5de73..840ba8ea0ac066 100644
--- a/llvm/unittests/ProfileData/MemProfTest.cpp
+++ b/llvm/unittests/ProfileData/MemProfTest.cpp
@@ -167,7 +167,7 @@ TEST(MemProf, FillsValue) {
     Records.insert({Pair.first, Pair.second});
   }
 
-  // Mock program psuedocode and expected memprof record contents.
+  // Mock program pseudocode and expected memprof record contents.
   //
   //                              AllocSite       CallSite
   // inline foo() { new(); }         Y               N