[PATCH] D157972: [DAG] SimplifyDemandedBits - add sra(shl(x,c1),c1) -> sign_extend_inreg(x) demanded elts fold

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: goldstein.w.n, pengfei, craig.topper.
Herald added subscribers: steven.zhang, atanasyan, hiraditya, arichardson, sdardis.
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Begin moving the sra(shl(x,c1),c1) -> sign_extend_inreg(x) fold inside SimplifyDemandedBits so we can recognize hidden splats with DemandedElts masks.

Because the c1 shift amount has multiple uses, hidden splats won't get simplified to a splat constant buildvector - meaning the existing fold in DAGCombiner::visitSRA can't fire as it won't see a uniform shift amount.

I had hoped to remove the DAGCombiner::visitSRA implementation entirely, but several targets (PPC + MIPS in particular) are missing ComputeNumSignBitsForTargetNode handling for their target nodes, making it tricky for superflous sign_extend_inreg nodes to be removed later on.

I also needed to add TLI preferSextInRegOfTruncate hook to help keep truncate(sign_extend_inreg(x)) vector patterns on X86 so we can use PACKSS more efficiently.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157972

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/X86/packss.ll

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