[PATCH] D157231: [SPARC][IAS] Add definitions for v9 State Registers

[Sergei Barannikov via Phabricator via llvm-commits]

barannikov88 added inline comments.


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Comment at: llvm/lib/Target/Sparc/SparcRegisterInfo.td:135
+def GL         : SparcCtrlReg<16, "GL">;
+def VER        : SparcCtrlReg<31, "VER">;
 
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koakuma wrote:
> barannikov88 wrote:
> > It looks like these registers are actually aliases to %asrXX (or vice versa). They should use the corresponding functionality instead of being redefined.
> > See RegAltNameIndex in Target.td and how other targets use it.
> > 
> The privileged ones are on a separate register file from the ASRs, so those need to be defined separately.
> 
> The unprivileged ones can be merged with the ASRs, however, I have a question about the handling of %tick/%asr4.
> The same register can be viewed through nonprivileged (rd %tick/rd %asr4) or privileged (rdpr %tick) instructions, however, since the two are modeled using different objects, it is quite difficult to make it usable by both instructions.
> Currently I am special casing it so that privileged TICK can also be read by `rd`. Is there any better way to do this or will this do for now?
I can't suggest anything better. Do other assemblers accept %asr1-6? The manual says there are only %asr7-31 (with 7-15 reserved for future use).
Note that adding TICK to ASRRegs allows it to be used in `wr` instruction, which isn't allowed by the manual (A.63 Write State Register).



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Comment at: llvm/test/MC/Sparc/sparc-special-registers.s:52
+
+! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
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RUN lines are conventionally at the start of a file. They can be combined with the existing RUN lines like this:
```
! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s --check-prefixes=CHECK,V8
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefixes=CHECK,V9
```
Note the --check-prefixes option.



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Comment at: llvm/test/MC/Sparc/sparcv9-instructions.s:425
         ! V9: rd %pc, %o7               ! encoding: [0x9f,0x41,0x40,0x00]
         rd %pc, %o7
+        ! V9: rd %asi, %g1              ! encoding: [0x83,0x40,0xc0,0x00]
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koakuma wrote:
> barannikov88 wrote:
> > IIUC all of these should complain about missing feature on V8. This can probably be done by adding some checks to validateTargetOperandClass or checkTargetMatchPredicate.
> > 
> How do I do this? Seems like in both functions I can only get the raw register number, I don't know how to recover the textual name (e.g whether it was originally referred to as %asi or %asr3)...
validateTargetOperandClass allows you to examine whatever you stored in SparcOperand. If the spelling is important, you can store that information there, see e.g. RegOp::RegisterKind.
The method should probably return Match_MissingFeature on failure.



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  https://reviews.llvm.org/D157231/new/

https://reviews.llvm.org/D157231