[PATCH] D157373: [RISCV] add a compress optimization for stack inst.

[lcvon via Phabricator via llvm-commits]

lcvon007 added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/stack-inst-compress.mir:13
+  entry:
+    %arr = alloca [517 x i32], align 4
+    call void @llvm.memset.p0.i64(ptr align 4 %arr, i8 0, i64 2068, i1 false)
----------------
wangpc wrote:
> lcvon007 wrote:
> > wangpc wrote:
> > > Nit: the LLVM IR in a MIR test can be just function stub, the function body can be removed.
> > Do you mean I only provide only a decalare  here? , like:
> > declare dso_local void @_Z18caller_small_stackv(), and the compiler will report error "basic block 'entry' is not defined in the function '_Z18caller_small_stackv'", so   
> >  does it need other change too or keep the body here as now?
> ```
> --- a/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
> +++ b/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
> @@ -10,23 +10,13 @@
>  --- |
>    define dso_local void @_Z18caller_small_stackv() {
>    entry:
> -    %arr = alloca [517 x i32], align 4
> -    call void @llvm.memset.p0.i64(ptr align 4 %arr, i8 0, i64 2068, i1 false)
> -    %arraydecay = getelementptr inbounds [517 x i32], ptr %arr, i64 0, i64 0
> -    call void @_Z6calleePi(ptr noundef %arraydecay)
>      ret void
>    }
>  
> -  declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
> -
>    declare dso_local void @_Z6calleePi(ptr noundef)
>  
>    define dso_local void @_Z19caller_larger_stackv() {
>    entry:
> -    %arr = alloca [1536 x i32], align 4
> -    call void @llvm.memset.p0.i64(ptr align 4 %arr, i8 0, i64 6144, i1 false)
> -    %arraydecay = getelementptr inbounds [1536 x i32], ptr %arr, i64 0, i64 0
> -    call void @_Z6calleePi(ptr noundef %arraydecay)
>      ret void
>    }
>  
> @@ -40,7 +30,7 @@ frameInfo:
>    hasCalls:        true
>    localFrameSize:  2068
>  stack:
> -  - { id: 0, name: arr, size: 2068, alignment: 4, local-offset: -2068 }
> +  - { id: 0, size: 2068, alignment: 4, local-offset: -2068 }
>    - { id: 1, type: spill-slot, size: 8, alignment: 8 }
>  machineFunctionInfo:
>    varArgsFrameIndex: 0
> @@ -93,7 +83,7 @@ body:             |
>      ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
>      renamable $x10 = LUI 1
>      renamable $x12 = ADDIW killed renamable $x10, -2028
> -    renamable $x10 = ADDI %stack.0.arr, 0
> +    renamable $x10 = ADDI %stack.0, 0
>      SD $x10, %stack.1, 0 :: (store (s64) into %stack.1)
>      renamable $x11 = COPY $x0
>      PseudoCALL target-flags(riscv-plt) &memset, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, implicit-def $x10
> @@ -115,7 +105,7 @@ frameInfo:
>    hasCalls:        true
>    localFrameSize:  6144
>  stack:
> -  - { id: 0, name: arr, size: 6144, alignment: 4, local-offset: -6144 }
> +  - { id: 0, size: 6144, alignment: 4, local-offset: -6144 }
>    - { id: 1, type: spill-slot, size: 8, alignment: 8 }
>  machineFunctionInfo:
>    varArgsFrameIndex: 0
> @@ -184,7 +174,7 @@ body:             |
>      ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
>      renamable $x10 = ADDI $x0, 3
>      renamable $x12 = SLLI killed renamable $x10, 11
> -    renamable $x10 = ADDI %stack.0.arr, 0
> +    renamable $x10 = ADDI %stack.0, 0
>      SD $x10, %stack.1, 0 :: (store (s64) into %stack.1)
>      renamable $x11 = COPY $x0
>      PseudoCALL target-flags(riscv-plt) &memset, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, implicit-def $x10
> ```
> 
> And if you are using `utils/update_mir_test_checks.py` to generate CHECKs, don't remove the output lines. Or you should remove the line 1:
> ```
> # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
> ```
> 
Done, I use update_mir_test_checks.py and remove some checkers, and I have removed the line 1 as you suggest, thanks very much.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157373/new/

https://reviews.llvm.org/D157373