[PATCH] D157847: [RISCV] Fix assertion when passing f64 vectors via integer registers
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 14 21:12:42 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGac00cca3d9c6: [RISCV] Fix assertion when passing f64 vectors via integer registers (authored by wangpc).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D157847/new/
https://reviews.llvm.org/D157847
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/pr64645.ll
Index: llvm/test/CodeGen/RISCV/pr64645.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/pr64645.ll
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32 < %s \
+; RUN: | FileCheck %s
+
+define <2 x double> @v2f64(<2 x double> %x, <2 x double> %y) nounwind {
+; CHECK-LABEL: v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: sw a4, 8(sp)
+; CHECK-NEXT: sw a5, 12(sp)
+; CHECK-NEXT: lw a4, 8(sp)
+; CHECK-NEXT: lw a5, 12(sp)
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: lw a0, 8(sp)
+; CHECK-NEXT: lw a1, 12(sp)
+; CHECK-NEXT: sw a6, 8(sp)
+; CHECK-NEXT: sw a7, 12(sp)
+; CHECK-NEXT: lw a6, 8(sp)
+; CHECK-NEXT: lw a7, 12(sp)
+; CHECK-NEXT: sw a2, 8(sp)
+; CHECK-NEXT: sw a3, 12(sp)
+; CHECK-NEXT: lw a2, 8(sp)
+; CHECK-NEXT: lw a3, 12(sp)
+; CHECK-NEXT: fadd.d a2, a2, a6
+; CHECK-NEXT: fadd.d a0, a0, a4
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: lw a0, 8(sp)
+; CHECK-NEXT: lw a1, 12(sp)
+; CHECK-NEXT: sw a2, 8(sp)
+; CHECK-NEXT: sw a3, 12(sp)
+; CHECK-NEXT: lw a2, 8(sp)
+; CHECK-NEXT: lw a3, 12(sp)
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %1 = fadd <2 x double> %x, %y
+ ret <2 x double> %1
+}
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15169,8 +15169,7 @@
// Handle passing f64 on RV32D with a soft float ABI or when floating point
// registers are exhausted.
if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) {
- assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
- "Can't lower f64 if it is split");
+ assert(PendingLocs.empty() && "Can't lower f64 if it is split");
// Depending on available argument GPRS, f64 may be passed in a pair of
// GPRs, split between a GPR and the stack, or passed completely on the
// stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
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