[PATCH] D157510: [RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:509
+
+def cv_tuimm2: Operand<XLenVT>, TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
+def cv_tuimm5: Operand<XLenVT>, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
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I think you can drop `Operand` from these.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:510
+def cv_tuimm2: Operand<XLenVT>, TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
+def cv_tuimm5: Operand<XLenVT>, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
+def cv_uimm10: Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
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Space before `:`


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:523
+
+multiclass PatCoreVBitManip <Intrinsic intr> {
+  def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
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Drop the space before `<`


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D157510/new/

https://reviews.llvm.org/D157510