[PATCH] D151414: [RISCV] Add Zvfhmin extension support for llvm RISCV backend.

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added a comment.

> Yes, I agree with merging these patches at the same time.
>
> But for the case `regalloc-last-chance-recoloring-failure.ll`, it uses the intirinsic `@llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64`, this intrinsic is not supported in zvfhmin, so cannot selected is the excepted action. By example we also cannot select `@llvm.riscv.vmulh.nxv1i64.i64` for ZVE64D, and any vector intrinsic for no V enable. I don't  think we should do promotion for intrinsic too.
> Actually target specific intrinsics basiclly comes from clang rvv-builtin. In https://reviews.llvm.org/D150253, any use of unsuportted builtin would cause a clang error. So there is no actual case will generate unsupportted intrinsic.

Thanks for the clarification. I agree with you now.


Repository:
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  https://reviews.llvm.org/D151414/new/

https://reviews.llvm.org/D151414