[PATCH] D134893: [LSR][TTI][RISCV] Add isAllowTerminatingConditionFoldingAfterLSR into TTI and enable it for RISC-V

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Reverse ping.  I applied this locally, and collected dynamic instruction counts for SPEC on a rv64gcv config.  The results didn't reveal any surprises or correctness issues.  Dynamic instruction count was very mildly improved overall (0.42% geomean improvement), with no regression larger than 0.25%.

I'd like to see this landed.  Can you rebase for a final LGTM?



================
Comment at: llvm/include/llvm/Analysis/TargetTransformInfo.h:691
+  /// Return true if LSR attempts to replace primary IV with other IV.
+  bool isAllowTerminatingConditionFoldingAfterLSR() const;
+
----------------
Please change to: shouldFoldTerminatingConditionAfterLSR


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D134893