[PATCH] D156909: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll:2787
+; RV32-NEXT:    sub a2, a0, a1
+; RV32-NEXT:    sltu a3, a0, a2
+; RV32-NEXT:    addi a3, a3, -1
----------------
craig.topper wrote:
> I think I'm missing how this change comes from this patch. The sltu+addi+and looks like an optimized select lowering. The old code use a branch for the select. It looks to me like all of the changes for this patch should be after select lowering.
That is a very good question!  

However, I think the answer is that it isn't actually select lowering, it's scheduling run slightly amuck.  If you look quite a bit further down the test diff, you see what appears to be a select-to-branch conversion going in the other direction.

I think what we actually have here is a massive rescheduling.  However, that would seem to require cross block scheduling, which too my knowledge, we don't have?  So maybe I'm still confused?  


================
Comment at: llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll:2897
 ; RV32-NEXT:    vs8r.v v8, (a3) # Unknown-size Folded Spill
-; RV32-NEXT:    sub a1, a0, a1
-; RV32-NEXT:    sltu a0, a0, a1
-; RV32-NEXT:    addi a0, a0, -1
-; RV32-NEXT:    and a0, a0, a1
+; RV32-NEXT:    bltu a0, a1, .LBB46_2
+; RV32-NEXT:  # %bb.1:
----------------
Here


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156909/new/

https://reviews.llvm.org/D156909