[llvm] 3a7a74c - [X86] truncateVectorWithPACKUS - use getZeroExtendInReg helper. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-08-14T16:50:13+01:00
New Revision: 3a7a74c8e54b05ffbfb24525de17ff54be80729c

URL: https://github.com/llvm/llvm-project/commit/3a7a74c8e54b05ffbfb24525de17ff54be80729c
DIFF: https://github.com/llvm/llvm-project/commit/3a7a74c8e54b05ffbfb24525de17ff54be80729c.diff

LOG: [X86] truncateVectorWithPACKUS - use getZeroExtendInReg helper. NFCI.

SelectionDAG::getZeroExtendInReg does exactly the same masking.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 547cc1d9456775..d65d15aac3bbbc 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -20090,17 +20090,14 @@ static SDValue truncateVectorWithPACK(unsigned Opcode, EVT DstVT, SDValue In,
   return truncateVectorWithPACK(Opcode, DstVT, Res, DL, DAG, Subtarget);
 }
 
-/// Truncate using ISD::AND mask and X86ISD::PACKUS.
+/// Truncate using inreg zero extension (AND mask) and X86ISD::PACKUS.
 /// e.g. trunc <8 x i32> X to <8 x i16> -->
 /// MaskX = X & 0xffff (clear high bits to prevent saturation)
 /// packus (extract_subv MaskX, 0), (extract_subv MaskX, 1)
 static SDValue truncateVectorWithPACKUS(EVT DstVT, SDValue In, const SDLoc &DL,
                                         const X86Subtarget &Subtarget,
                                         SelectionDAG &DAG) {
-  EVT SrcVT = In.getValueType();
-  APInt Mask = APInt::getLowBitsSet(SrcVT.getScalarSizeInBits(),
-                                    DstVT.getScalarSizeInBits());
-  In = DAG.getNode(ISD::AND, DL, SrcVT, In, DAG.getConstant(Mask, DL, SrcVT));
+  In = DAG.getZeroExtendInReg(In, DL, DstVT);
   return truncateVectorWithPACK(X86ISD::PACKUS, DstVT, In, DL, DAG, Subtarget);
 }