[llvm] 6551cfa - [CodeGen] Set regunitmasks for leaf regs to all instead of none
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 14 07:22:41 PDT 2023
Author: Jay Foad
Date: 2023-08-14T15:22:35+01:00
New Revision: 6551cfa8eb2960dbc27e2882b204c4e0aff0109f
URL: https://github.com/llvm/llvm-project/commit/6551cfa8eb2960dbc27e2882b204c4e0aff0109f
DIFF: https://github.com/llvm/llvm-project/commit/6551cfa8eb2960dbc27e2882b204c4e0aff0109f.diff
LOG: [CodeGen] Set regunitmasks for leaf regs to all instead of none
This simplifies every use of MCRegUnitMaskIterator.
Differential Revision: https://reviews.llvm.org/D157864
Added:
Modified:
llvm/include/llvm/CodeGen/LiveRegUnits.h
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/RDFRegisters.cpp
llvm/utils/TableGen/CodeGenRegisters.cpp
llvm/utils/TableGen/RegisterInfoEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/LiveRegUnits.h b/llvm/include/llvm/CodeGen/LiveRegUnits.h
index a750d5dec54633..d554493e629ed3 100644
--- a/llvm/include/llvm/CodeGen/LiveRegUnits.h
+++ b/llvm/include/llvm/CodeGen/LiveRegUnits.h
@@ -93,7 +93,7 @@ class LiveRegUnits {
void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) {
for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
LaneBitmask UnitMask = (*Unit).second;
- if (UnitMask.none() || (UnitMask & Mask).any())
+ if ((UnitMask & Mask).any())
Units.set((*Unit).first);
}
}
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 8fda4c3e3e83f8..b4cbb93d758ef2 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -1704,10 +1704,9 @@ static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
for (auto U : UsedOpsInCopy) {
Register SrcReg = MI->getOperand(U).getReg();
LaneBitmask Mask;
- for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S) {
+ for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S)
Mask |= (*S).second;
- }
- SuccBB->addLiveIn(SrcReg, Mask.any() ? Mask : LaneBitmask::getAll());
+ SuccBB->addLiveIn(SrcReg, Mask);
}
SuccBB->sortUniqueLiveIns();
}
diff --git a/llvm/lib/CodeGen/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp
index 90520c4c3c71e6..7ce00a66b3ae6c 100644
--- a/llvm/lib/CodeGen/RDFRegisters.cpp
+++ b/llvm/lib/CodeGen/RDFRegisters.cpp
@@ -61,14 +61,7 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
std::pair<uint32_t, LaneBitmask> P = *I;
UnitInfo &UI = UnitInfos[P.first];
UI.Reg = F;
- if (P.second.any()) {
- UI.Mask = P.second;
- } else {
- if (const TargetRegisterClass *RC = RegInfos[F].RegClass)
- UI.Mask = RC->LaneMask;
- else
- UI.Mask = LaneBitmask::getAll();
- }
+ UI.Mask = P.second;
}
}
}
@@ -141,7 +134,7 @@ std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const {
return Units; // Empty
for (MCRegUnitMaskIterator UM(RR.idx(), &TRI); UM.isValid(); ++UM) {
auto [U, M] = *UM;
- if (M.none() || (M & RR.Mask).any())
+ if ((M & RR.Mask).any())
Units.insert(U);
}
return Units;
@@ -200,13 +193,6 @@ bool PhysicalRegisterInfo::equal_to(RegisterRef A, RegisterRef B) const {
auto [AReg, AMask] = *AI;
auto [BReg, BMask] = *BI;
- // Lane masks are "none" for units that don't correspond to subregs
- // e.g. a single unit in a leaf register, or aliased unit.
- if (AMask.none())
- AMask = LaneBitmask::getAll();
- if (BMask.none())
- BMask = LaneBitmask::getAll();
-
// If both iterators point to a unit contained in both A and B, then
// compare the units.
if ((AMask & A.Mask).any() && (BMask & B.Mask).any()) {
@@ -245,13 +231,6 @@ bool PhysicalRegisterInfo::less(RegisterRef A, RegisterRef B) const {
auto [AReg, AMask] = *AI;
auto [BReg, BMask] = *BI;
- // Lane masks are "none" for units that don't correspond to subregs
- // e.g. a single unit in a leaf register, or aliased unit.
- if (AMask.none())
- AMask = LaneBitmask::getAll();
- if (BMask.none())
- BMask = LaneBitmask::getAll();
-
// If both iterators point to a unit contained in both A and B, then
// compare the units.
if ((AMask & A.Mask).any() && (BMask & B.Mask).any()) {
@@ -303,7 +282,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
std::pair<uint32_t, LaneBitmask> P = *U;
- if (P.second.none() || (P.second & RR.Mask).any())
+ if ((P.second & RR.Mask).any())
if (Units.test(P.first))
return true;
}
@@ -318,7 +297,7 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
std::pair<uint32_t, LaneBitmask> P = *U;
- if (P.second.none() || (P.second & RR.Mask).any())
+ if ((P.second & RR.Mask).any())
if (!Units.test(P.first))
return false;
}
@@ -333,7 +312,7 @@ RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
std::pair<uint32_t, LaneBitmask> P = *U;
- if (P.second.none() || (P.second & RR.Mask).any())
+ if ((P.second & RR.Mask).any())
Units.set(P.first);
}
return *this;
@@ -407,7 +386,7 @@ RegisterRef RegisterAggr::makeRegRef() const {
for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) {
std::pair<uint32_t, LaneBitmask> P = *I;
if (Units.test(P.first))
- M |= P.second.none() ? LaneBitmask::getAll() : P.second;
+ M |= P.second;
}
return RegisterRef(F, M);
}
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 74fb80610b9c17..b8dde6e946a422 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -2123,8 +2123,8 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
for (auto &Register : Registers) {
// Create an initial lane mask for all register units.
const auto &RegUnits = Register.getRegUnits();
- CodeGenRegister::RegUnitLaneMaskList
- RegUnitLaneMasks(RegUnits.count(), LaneBitmask::getNone());
+ CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks(
+ RegUnits.count(), LaneBitmask::getAll());
// Iterate through SubRegisters.
typedef CodeGenRegister::SubRegMap SubRegMap;
const SubRegMap &SubRegs = Register.getSubRegs();
@@ -2143,7 +2143,7 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
unsigned u = 0;
for (unsigned RU : RegUnits) {
if (SUI == RU) {
- RegUnitLaneMasks[u] |= LaneMask;
+ RegUnitLaneMasks[u] &= LaneMask;
assert(!Found);
Found = true;
}
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 7e537e07a5d234..7c0d024959c5a1 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -931,12 +931,6 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
assert(LaneMaskVec.empty());
llvm::append_range(LaneMaskVec, RUMasks);
- // Terminator mask should not be used inside of the list.
-#ifndef NDEBUG
- for (LaneBitmask M : LaneMaskVec) {
- assert(!M.all() && "terminator mask should not be part of the list");
- }
-#endif
LaneMaskSeqs.add(LaneMaskVec);
}
@@ -956,6 +950,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the shared table of regunit lane mask sequences.
OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n";
+ // TODO: Omit the terminator since it is never used. The length of this list
+ // is known implicitly from the corresponding reg unit list.
LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()");
OS << "};\n\n";
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