[PATCH] D157832: [RISCV] Add tune features of preferred function/loop align

[Wang Pengcheng via Phabricator via llvm-commits]

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D144048 <https://reviews.llvm.org/D144048> has added preferred function and loop alignment to
RISCVSubtarget, but now we need to set them manually for
different processors.

Tune features that set preferred function/loop align to
[2, 256] bytes (align 1 is not here since the min align is
2 and the max align is 256 bytes though I don't know if it
is possible for potential μ-arch) are added. These features
can be used in processor definitions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157832

Files:
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/align-loops.ll
  llvm/test/CodeGen/RISCV/align.ll


Index: llvm/test/CodeGen/RISCV/align.ll
===================================================================
--- llvm/test/CodeGen/RISCV/align.ll
+++ llvm/test/CodeGen/RISCV/align.ll
@@ -2,6 +2,8 @@
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32C
+; RUN: llc -mtriple=riscv32 -mattr=+pref-func-align-32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=ALIGN-32
 ; RUN: llc -filetype=obj -mtriple=riscv32 < %s -o %t
 ; RUN: llvm-readelf -S %t | FileCheck %s --check-prefixes=SEC,SEC-I
 ; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+c < %s -o %t
@@ -16,6 +18,8 @@
 ;RV32I: foo:
 ;RV32C: .p2align 1
 ;RV32C: foo:
+;ALIGN-32: .p2align 5
+;ALIGN-32: foo:
 entry:
   ret void
 }
Index: llvm/test/CodeGen/RISCV/align-loops.ll
===================================================================
--- llvm/test/CodeGen/RISCV/align-loops.ll
+++ llvm/test/CodeGen/RISCV/align-loops.ll
@@ -1,6 +1,8 @@
 ; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
 ; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s -check-prefix=ALIGN_16
 ; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileCheck %s -check-prefix=ALIGN_32
+; RUN: llc < %s -mtriple=riscv64 -mattr=+pref-loop-align-16 | FileCheck %s -check-prefix=ALIGN_16
+; RUN: llc < %s -mtriple=riscv64 -mattr=+pref-loop-align-32 | FileCheck %s -check-prefix=ALIGN_32
 
 declare void @foo()
 
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -925,3 +925,13 @@
     "AllowTaggedGlobals",
     "true", "Use an instruction sequence for taking the address of a global "
     "that allows a memory tag in the upper address bits">;
+
+foreach i = {1-8} in {
+  defvar align = !shl(1, i);
+  def TunePrefFunctionAlignment # align :
+      SubtargetFeature<"pref-func-align-" # align, "PrefFunctionAlignment",
+                       "Align(" # align # ")", "Set preferred function alignment to " # align # " bytes">;
+  def TunePrefLoopAlignment # align :
+      SubtargetFeature<"pref-loop-align-" # align, "PrefLoopAlignment",
+                       "Align(" # align # ")", "Set preferred loop alignment to " # align # " bytes">;
+}


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