[llvm] 8a98f24 - [RISCV] Truncate constants to EltSize when combine store of BUILD_VECTOR

[via llvm-commits]

Author: wangpc
Date: 2023-08-14T10:55:53+08:00
New Revision: 8a98f24ec51ea12a50f1e63dd030482e387534a1

URL: https://github.com/llvm/llvm-project/commit/8a98f24ec51ea12a50f1e63dd030482e387534a1
DIFF: https://github.com/llvm/llvm-project/commit/8a98f24ec51ea12a50f1e63dd030482e387534a1.diff

LOG: [RISCV] Truncate constants to EltSize when combine store of BUILD_VECTOR

The constants can be with larger bit width, so we need to truncate
them to EltSize or we will exceed the width of fixed-length vector.

Fixes #64588

Reviewed By: luke, craig.topper, bjope, michaelmaitland

Differential Revision: https://reviews.llvm.org/D157603

Added: 
    llvm/test/CodeGen/RISCV/rvv/pr64588.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 22b850da274729..2d4cfe67e170bc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13479,11 +13479,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
         ISD::isBuildVectorOfConstantSDNodes(Val.getNode())) {
       // Get the constant vector bits
       APInt NewC(Val.getValueSizeInBits(), 0);
+      uint64_t EltSize = Val.getScalarValueSizeInBits();
       for (unsigned i = 0; i < Val.getNumOperands(); i++) {
         if (Val.getOperand(i).isUndef())
           continue;
-        NewC.insertBits(Val.getConstantOperandAPInt(i),
-                        i * Val.getScalarValueSizeInBits());
+        NewC.insertBits(Val.getConstantOperandAPInt(i).trunc(EltSize),
+                        i * EltSize);
       }
       MVT NewVT = MVT::getIntegerVT(MemVT.getSizeInBits());
 

diff  --git a/llvm/test/CodeGen/RISCV/rvv/pr64588.ll b/llvm/test/CodeGen/RISCV/rvv/pr64588.ll
new file mode 100644
index 00000000000000..49600f06717411
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/pr64588.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple riscv64 -mattr=+zve64x | FileCheck %s
+
+define void @bar(ptr %p) {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sd zero, 0(a0)
+; CHECK-NEXT:    sd zero, 8(a0)
+; CHECK-NEXT:    ret
+  %v = insertelement <64 x i64> zeroinitializer, i64 0, i32 0
+  %trunc = trunc <64 x i64> %v to <64 x i1>
+  %p1 = getelementptr i8, ptr %p, i32 0
+  %p2 = getelementptr i8, ptr %p, i32 8
+  store <64 x i1> %trunc, ptr %p1
+  store <8 x i8> zeroinitializer, ptr %p2
+  ret void
+}