[PATCH] D156685: [RISCV] Match ext + ext + srem + trunc to vrem.vv

[Vettel via Phabricator via llvm-commits]

LWenH added a comment.

In D156685#4582348 <https://reviews.llvm.org/D156685#4582348>, @craig.topper wrote:

> In D156685#4576001 <https://reviews.llvm.org/D156685#4576001>, @LWenH wrote:
>
>> Address @craig.topper and @Jim 's comments. Update and add  precommit test for this patch.
>>
>> Actually, I think these signed operation can't be removed before the instruction selection phase. These signed extension and trunc operation pair in LLVM system is to prevent Undefined Behavior. Taking an example, -128 % -1 will lead to the Undefined Behaviour(overflowed) under the i8 type in LLVM IR, but this won't happen for i32. So LLVM first extend this to i32 to prevent the UB.  For the unsigned, such pattern can be able to removed during the instcombine pass, this is because the urem operation won't lead to the overflowed in LLVM. For RVV, such overflow operation has been defined in the spec and have the determined output. For example, base on the spec, for the i8 type, -128 % -1 actually have 0 as the output result. So, I'm thinking for the rvv backend, we can remove such pattern to shrink the codesize.
>
> I agree they can't be removed before the instruction selection phase. Can you explain this in the commit message so that it will be in the git log when this is committed?

Address @craig.topper coments, update patch description about matching this pattern in the instruction selection phase. Thank you for your suggestion and the help with submitting the precommit test!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156685/new/

https://reviews.llvm.org/D156685