[llvm] 512a6c5 - [X86] combineToExtendBoolVectorInReg - don't use changeVectorElementType to create the bool vector type

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-08-13T11:18:59+01:00
New Revision: 512a6c50e87c1956c028daf3317b07b3aa0e309f

URL: https://github.com/llvm/llvm-project/commit/512a6c50e87c1956c028daf3317b07b3aa0e309f
DIFF: https://github.com/llvm/llvm-project/commit/512a6c50e87c1956c028daf3317b07b3aa0e309f.diff

LOG: [X86] combineToExtendBoolVectorInReg - don't use changeVectorElementType to create the bool vector type

Converting a (simple) vXf32 type to a vXi1 type isn't guaranteed to be simple, causing the MVT type to be invalid.

Fixes #64627

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/vector-reduce-fadd.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 727d87c3def0bc..30852a7f75f2c4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -44137,7 +44137,7 @@ static SDValue combineToExtendBoolVectorInReg(
   Vec = DAG.getNode(ISD::AND, DL, VT, Vec, BitMask);
 
   // Compare against the bitmask and extend the result.
-  EVT CCVT = VT.changeVectorElementType(MVT::i1);
+  EVT CCVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElts);
   Vec = DAG.getSetCC(DL, CCVT, Vec, BitMask, ISD::SETEQ);
   Vec = DAG.getSExtOrTrunc(Vec, DL, VT);
 

diff  --git a/llvm/test/CodeGen/X86/vector-reduce-fadd.ll b/llvm/test/CodeGen/X86/vector-reduce-fadd.ll
index 883806d304d60e..9dd2a045087dad 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fadd.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fadd.ll
@@ -1898,6 +1898,28 @@ define double @test_v16f64_undef(<16 x double> %a0) {
   ret double %1
 }
 
+define float @PR64627() {
+; SSE-LABEL: PR64627:
+; SSE:       # %bb.0:
+; SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: PR64627:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-NEXT:    retq
+;
+; AVX512-LABEL: PR64627:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX512-NEXT:    retq
+  %1 = bitcast i5 0 to <5 x i1>
+  %2 = select <5 x i1> %1, <5 x float> zeroinitializer, <5 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
+  %3 = call float @llvm.vector.reduce.fadd.v5f32(float -0.0, <5 x float> %2)
+  ret float %3
+}
+declare float @llvm.vector.reduce.fadd.v5f32(float, <5 x float>)
+
 declare float @llvm.vector.reduce.fadd.f32.v2f32(float, <2 x float>)
 declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
 declare float @llvm.vector.reduce.fadd.f32.v8f32(float, <8 x float>)