[llvm] da56750 - [RISCV] Change naming of vector pseudos with scalar FP operand.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 12 11:27:39 PDT 2023
Author: Craig Topper
Date: 2023-08-12T11:20:47-07:00
New Revision: da56750f82a60b5872679424fc6ae78a42c786a0
URL: https://github.com/llvm/llvm-project/commit/da56750f82a60b5872679424fc6ae78a42c786a0
DIFF: https://github.com/llvm/llvm-project/commit/da56750f82a60b5872679424fc6ae78a42c786a0.diff
LOG: [RISCV] Change naming of vector pseudos with scalar FP operand.
We need a pseudo for each scalar FP register class. Previously
we distinquished the pseudos by naming them with F16, F32, F64, or
BF16 in place of the F in the normal instruction name.
Because these strings can appear in other parts of the name we had
to do things like matching "_VBF16" to "_VF".
This patch replaces the F16, F32, F64 strings with FPR16, FPR32, and
FPR64. We also use FPR16 for BF16 since that is the scalar register
class for bf16.
Since the FPR16/32/64 string does not anywhere else in the pseudo
names, we can use this to simplify the string replacements. This
also allows us to simplify some BF16 related code.
Reviewed By: wangpc
Differential Revision: https://reviews.llvm.org/D157749
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 8b419c720022b3..aa73c1eb760ef6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2194,9 +2194,9 @@ std::string RISCVInstrInfo::createMIROperandComment(
case CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
#define CASE_VFMA_SPLATS(OP) \
- CASE_VFMA_OPCODE_LMULS_MF4(OP, VF16): \
- case CASE_VFMA_OPCODE_LMULS_MF2(OP, VF32): \
- case CASE_VFMA_OPCODE_LMULS_M1(OP, VF64)
+ CASE_VFMA_OPCODE_LMULS_MF4(OP, VFPR16): \
+ case CASE_VFMA_OPCODE_LMULS_MF2(OP, VFPR32): \
+ case CASE_VFMA_OPCODE_LMULS_M1(OP, VFPR64)
// clang-format on
bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
@@ -2357,9 +2357,9 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \
- CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VF16) \
- CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VF32) \
- CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VF64)
+ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16) \
+ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32) \
+ CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64)
MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
bool NewMI,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index ac82cb5206167a..dce03b6a52cfac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -115,16 +115,9 @@ class PseudoToVInst<string PseudoInst> {
["_E32", ""],
["_E16", ""],
["_E8", ""],
- ["_F64", "_F"],
- ["_F32", "_F"],
- ["_F16", "_F"],
- ["_VF64", "_VF"],
- ["_VF32", "_VF"],
- ["_VF16", "_VF"],
- ["_VBF16", "_VF"],
- ["_WF64", "_WF"],
- ["_WF32", "_WF"],
- ["_WF16", "_WF"],
+ ["FPR64", "F"],
+ ["FPR32", "F"],
+ ["FPR16", "F"],
["_TU", ""],
["_TIED", ""],
["_MASK", ""],
@@ -205,15 +198,7 @@ class MxSet<int eew> {
class FPR_Info<int sew> {
RegisterClass fprclass = !cast<RegisterClass>("FPR" # sew);
- string FX = "F" # sew;
- int SEW = sew;
- list<LMULInfo> MxList = MxSet<sew>.m;
- list<LMULInfo> MxListFW = !if(!eq(sew, 64), [], !listremove(MxList, [V_M8]));
-}
-
-class BFPR_Info<int sew> {
- RegisterClass fprclass = !cast<RegisterClass>("FPR" # sew);
- string FX = "BF" # sew;
+ string FX = "FPR" # sew;
int SEW = sew;
list<LMULInfo> MxList = MxSet<sew>.m;
list<LMULInfo> MxListFW = !if(!eq(sew, 64), [], !listremove(MxList, [V_M8]));
@@ -223,7 +208,8 @@ def SCALAR_F16 : FPR_Info<16>;
def SCALAR_F32 : FPR_Info<32>;
def SCALAR_F64 : FPR_Info<64>;
-def SCALAR_BF16 : BFPR_Info<16>;
+// BF16 uses the same register class as F16.
+def SCALAR_BF16 : FPR_Info<16>;
defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
@@ -286,10 +272,10 @@ class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
OutPatFrag AVL = VLMax;
string ScalarSuffix = !cond(!eq(Scal, XLenVT) : "X",
- !eq(Scal, f16) : "F16",
- !eq(Scal, bf16) : "BF16",
- !eq(Scal, f32) : "F32",
- !eq(Scal, f64) : "F64");
+ !eq(Scal, f16) : "FPR16",
+ !eq(Scal, bf16) : "FPR16",
+ !eq(Scal, f32) : "FPR32",
+ !eq(Scal, f64) : "FPR64");
}
class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,
@@ -3103,12 +3089,6 @@ multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f> {
m.vrclass, m, constraint>;
}
-multiclass VPseudoTernaryW_VF_BF_RM<LMULInfo m, BFPR_Info f> {
- defvar constraint = "@earlyclobber $rd";
- defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, f.fprclass,
- m.vrclass, m, constraint>;
-}
-
multiclass VPseudoVSLDVWithPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
@@ -3238,7 +3218,7 @@ multiclass VPseudoVWMAC_VV_VF_BF_RM {
defvar ReadVFWMulAddV_MX = !cast<SchedRead>("ReadVFWMulAddV_" # mx);
defvar ReadVFWMulAddF_MX = !cast<SchedRead>("ReadVFWMulAddF_" # mx);
- defm "" : VPseudoTernaryW_VF_BF_RM<m, f>,
+ defm "" : VPseudoTernaryW_VF_RM<m, f>,
Sched<[WriteVFWMulAddF_MX, ReadVFWMulAddV_MX,
ReadVFWMulAddF_MX, ReadVFWMulAddV_MX, ReadVMask]>;
}
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