[PATCH] D157581: [SelectionDAG][X86][WIP] Don't always seperate conditions in `(br (and/or cond0, cond1))` into seperate branches

Noah Goldstein via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 11 14:46:02 PDT 2023

goldstein.w.n added a comment.

In D157581#4575461 <https://reviews.llvm.org/D157581#4575461>, @craig.topper wrote:

> In D157581#4575458 <https://reviews.llvm.org/D157581#4575458>, @goldstein.w.n wrote:
>> In D157581#4575452 <https://reviews.llvm.org/D157581#4575452>, @craig.topper wrote:
>>> I have wondered in the past if this should be done by codegenprepare instead of SelectionDAGBuilder. I believe codegenprepare does it for fast isel.
>>> The current code in SelectionDAGBuilder doesn’t sink an AND so it blocks forming TEST instructions. CodegenPrepare already knows how to sink AND to be near compare.
>> Is in break up the branches in IR instead then let selectiondagbuilder just translate 1-1?
>> I see `splitBranchCondition` in CodeGenPrepare. You'd suggest there?
> Yep that looks like the code. I see there is a FIXME there to remove the SelectionDAGBuilder code. If I remember right CodeGenPrepare creates the branches in a different order than SelectionDAGBuilder does. Whether that's good or bad I don't know, just that it's different.

So the splitting logic in `CodeGenPrepare` seems to only be valid under `TM->Options.EnableFastISel`, otherwise starting running into:


  rG LLVM Github Monorepo



More information about the llvm-commits mailing list