[llvm] 7e9a1b1 - [RISCV] Remove trailing whitespace from some .td files.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 11 12:29:26 PDT 2023
Author: Craig Topper
Date: 2023-08-11T12:29:20-07:00
New Revision: 7e9a1b18cbe28c3fa047fbdc28589e5b955a0d64
URL: https://github.com/llvm/llvm-project/commit/7e9a1b18cbe28c3fa047fbdc28589e5b955a0d64
DIFF: https://github.com/llvm/llvm-project/commit/7e9a1b18cbe28c3fa047fbdc28589e5b955a0d64.diff
LOG: [RISCV] Remove trailing whitespace from some .td files.
Most of this is in fairly recent vector bf16 related changes.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 245e46ef95cf37..ac82cb5206167a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -379,7 +379,7 @@ defset list<VTypeInfo> AllBFloatVectors = {
}
def VBF16M1: VTypeInfo<vbfloat16m1_t, vbool16_t, 16, VR, V_M1, bf16, FPR16>;
}
-
+
defset list<GroupVTypeInfo> GroupBFloatVectors = {
def VBF16M2: GroupVTypeInfo<vbfloat16m2_t, vbfloat16m1_t, vbool8_t, 16,
VRM2, V_M2, bf16, FPR16>;
@@ -524,7 +524,7 @@ defset list<VTypeInfoToWide> AllWidenableIntToFloatVectors = {
def : VTypeInfoToWide<VI32M2, VF64M4>;
def : VTypeInfoToWide<VI32M4, VF64M8>;
}
-
+
defset list<VTypeInfoToWide> AllWidenableBFloatToFloatVectors = {
def : VTypeInfoToWide<VBF16MF4, VF32MF2>;
def : VTypeInfoToWide<VBF16MF2, VF32M1>;
@@ -3005,7 +3005,7 @@ multiclass VPseudoTernaryWithTailPolicyRoundingMode<VReg RetClass,
defvar mx = MInfo.MX;
let isCommutable = Commutable in
def "_" # mx # "_E" # sew
- : VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class,
+ : VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class,
Op2Class, Constraint>;
def "_" # mx # "_E" # sew # "_MASK"
: VPseudoTernaryMaskPolicyRoundingMode<RetClass, Op1Class,
@@ -3225,19 +3225,19 @@ multiclass VPseudoVWMAC_VV_VF_BF_RM {
defvar mx = m.MX;
defvar WriteVFWMulAddV_MX = !cast<SchedWrite>("WriteVFWMulAddV_" # mx);
defvar ReadVFWMulAddV_MX = !cast<SchedRead>("ReadVFWMulAddV_" # mx);
-
+
defm "" : VPseudoTernaryW_VV_RM<m>,
Sched<[WriteVFWMulAddV_MX, ReadVFWMulAddV_MX,
ReadVFWMulAddV_MX, ReadVFWMulAddV_MX, ReadVMask]>;
}
-
+
foreach f = BFPListW in {
foreach m = f.MxListFW in {
defvar mx = m.MX;
defvar WriteVFWMulAddF_MX = !cast<SchedWrite>("WriteVFWMulAddF_" # mx);
defvar ReadVFWMulAddV_MX = !cast<SchedRead>("ReadVFWMulAddV_" # mx);
defvar ReadVFWMulAddF_MX = !cast<SchedRead>("ReadVFWMulAddF_" # mx);
-
+
defm "" : VPseudoTernaryW_VF_BF_RM<m, f>,
Sched<[WriteVFWMulAddF_MX, ReadVFWMulAddV_MX,
ReadVFWMulAddF_MX, ReadVFWMulAddV_MX, ReadVMask]>;
@@ -3335,7 +3335,7 @@ multiclass VPseudoVFRED_VS_RM {
defvar mx = m.MX;
foreach e = SchedSEWSet<mx, isF=1>.val in {
defm _VS
- : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
+ : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
V_M1.vrclass, m, e>,
SchedReduction<"WriteVFRedV_From", "ReadVFRedV", mx, e>;
}
@@ -5995,7 +5995,7 @@ foreach vti = AllIntegerVectors in {
GPR:$vl,
vti.Log2SEW,
(XLenVT timm:$policy))>;
-
+
// Match VSUB with a small immediate to vadd.vi by negating the immediate.
def : Pat<(vti.Vector (int_riscv_vsub (vti.Vector (undef)),
(vti.Vector vti.RegClass:$rs1),
@@ -6802,7 +6802,7 @@ foreach vti = AllVectors in {
VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
$passthru, $rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
-
+
// vmv.v.x/vmv.v.i are handled in RISCInstrVInstrInfoVVLPatterns.td
}
}
@@ -6885,7 +6885,7 @@ defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwsub_w", "PseudoVFWSUB",
//===----------------------------------------------------------------------===//
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
//===----------------------------------------------------------------------===//
-defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfmul", "PseudoVFMUL",
+defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfmul", "PseudoVFMUL",
AllFloatVectors>;
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfdiv", "PseudoVFDIV",
AllFloatVectors, isSEWAware=1>;
@@ -6920,9 +6920,9 @@ defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmacc", "PseudoVFWNMACC",
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmsac", "PseudoVFWMSAC",
AllWidenableFloatVectors>;
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC",
- AllWidenableFloatVectors>;
+ AllWidenableFloatVectors>;
let Predicates = [HasStdExtZvfbfwma] in
-defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16",
+defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16",
AllWidenableBFloatToFloatVectors>;
//===----------------------------------------------------------------------===//
@@ -7028,7 +7028,7 @@ defm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_x_f_v", "PseudoVFWCVT_RTZ_X_F">
defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU">;
defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X">;
defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F">;
-defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v",
+defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v",
"PseudoVFWCVTBF16_F_F">;
//===----------------------------------------------------------------------===//
@@ -7041,7 +7041,7 @@ defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F">
defm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU">;
defm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X">;
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F">;
-defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
+defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
"PseudoVFNCVTBF16_F_F">;
defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index d16db5ce754391..be132e1f066158 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -893,7 +893,7 @@ foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VBF16M1, VF16M1, VF32M1, VF64M1] i
defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
vti.RegClass>;
foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors, GroupBFloatVectors) in
- let Predicates = GetVTypePredicates<vti>.Predicates in
+ let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
vti.RegClass>;
foreach mti = AllMasks in
@@ -1146,7 +1146,7 @@ foreach mti = AllMasks in {
// Handle rvv_vnot the same as the vmnot.m pseudoinstruction.
def : Pat<(mti.Mask (rvv_vnot VR:$rs)),
(!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX)
- VR:$rs, VR:$rs, mti.AVL, mti.Log2SEW)>;
+ VR:$rs, VR:$rs, mti.AVL, mti.Log2SEW)>;
}
}
@@ -1303,7 +1303,7 @@ foreach vti = AllFloatVectors in {
(!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
-
+
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (fneg vti.RegClass:$rs2)))),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index ac9187838c206c..cf7de457246796 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2220,7 +2220,7 @@ defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU", IntegerVectorsExceptI6
// vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*.
let Predicates = [HasVInstructionsFullMultiply] in {
defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH", I64IntegerVectors>;
- defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU", I64IntegerVectors>;
+ defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU", I64IntegerVectors>;
}
// 11.11. Vector Integer Divide Instructions
@@ -2463,9 +2463,9 @@ foreach vti = AllFloatVectors in {
(!cast<Instruction>("PseudoVFROUND_NOEXCEPT_V_" # vti.LMul.MX #"_MASK")
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
-
+
// 14.14. Vector Floating-Point Classify Instruction
- def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2),
+ def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(!cast<Instruction>("PseudoVFCLASS_V_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;
@@ -2770,7 +2770,7 @@ foreach vti = AllIntegerVectors in {
(!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
vti.RegClass:$merge,
(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
-
+
def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
vti.RegClass:$rs1,
vti.RegClass:$merge,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index fd9a75a385cb51..152c10c7e97643 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -445,10 +445,10 @@ let Predicates = [HasVendorXCVsimd, IsRV32],
def CV_PACK : CVSIMDRR<0b11110, 0, 0, 0b000, "cv.pack">;
def CV_PACK_H : CVSIMDRR<0b11110, 0, 1, 0b000, "cv.pack.h">;
-
+
def CV_PACKHI_B : CVSIMDRRWb<0b11111, 0, 1, 0b001, "cv.packhi.b">;
def CV_PACKLO_B : CVSIMDRRWb<0b11111, 0, 0, 0b001, "cv.packlo.b">;
-
+
defm CMPEQ : CVSIMDBinarySigned<0b00000, 1, 0, "cmpeq">;
defm CMPNE : CVSIMDBinarySigned<0b00001, 1, 0, "cmpne">;
defm CMPGT : CVSIMDBinarySigned<0b00010, 1, 0, "cmpgt">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index 94a36a5279a4f5..f3809f2abff695 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -16,12 +16,12 @@
//===----------------------------------------------------------------------===//
// RISC-V specific DAG Nodes.
//===----------------------------------------------------------------------===//
-
+
def SDT_RISCVFP_ROUND_BF16
: SDTypeProfile<1, 1, [SDTCisVT<0, bf16>, SDTCisVT<1, f32>]>;
def SDT_RISCVFP_EXTEND_BF16
: SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, bf16>]>;
-
+
def riscv_fpround_bf16
: SDNode<"RISCVISD::FP_ROUND_BF16", SDT_RISCVFP_ROUND_BF16>;
def riscv_fpextend_bf16
@@ -41,7 +41,7 @@ def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16
//===----------------------------------------------------------------------===//
// Pseudo-instructions and codegen patterns
//===----------------------------------------------------------------------===//
-
+
let Predicates = [HasStdExtZfbfmin] in {
/// Loads
def : LdPat<load, FLH, bf16>;
@@ -51,9 +51,9 @@ def : StPat<store, FSH, FPR16, bf16>;
/// Float conversion operations
// f32 -> bf16, bf16 -> f32
-def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
+def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
(FCVT_BF16_S FPR32:$rs1, FRM_DYN)>;
-def : Pat<(riscv_fpextend_bf16 (bf16 FPR16:$rs1)),
+def : Pat<(riscv_fpextend_bf16 (bf16 FPR16:$rs1)),
(FCVT_S_BF16 FPR16:$rs1, FRM_DYN)>;
// Moves (no conversion)
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