[PATCH] D146872: [1/11][IR] Permit load/store/alloca for struct of the same scalable vector type

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll:18-19
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
+; CHECK-NEXT:    addi a2, a0, 8
+; CHECK-NEXT:    vl1re64.v v8, (a2)
+; CHECK-NEXT:    vl1re64.v v9, (a0)
----------------
paulwalker-arm wrote:
> Apologies for any naivety here but is the code generation here correct?  I'm trying to figure out the patch's objective because it looks like it has enable support within the IR but ignored code generation.  My interpretation of this output is that whilst it correctly allocates the vscale relative stack space:
> ```
> csrrs a2, vlenb, zero
> slli a2, a2, 1
> sub sp, sp, a2
> ```
> it then simply falls back to fixed length offsets when accessing it:
> ```
> addi a2, a0, 8
> vl1re64.v v8, (a2)
> ```
> Is my interpretation here correct? or have I misunderstood something?
I've pushed a test for SVE under https://reviews.llvm.org/rGac2a7637fe74 which shows similar behaviour.  So now I'm pretty sure this is just broken.  I'm working on a fix that I'll post later, probably Monday.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146872/new/

https://reviews.llvm.org/D146872