[llvm] 8f18cf7 - AMDGPU: Check for implicit defs before constant folding instruction
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 11 07:36:13 PDT 2023
Author: Matt Arsenault
Date: 2023-08-11T10:29:53-04:00
New Revision: 8f18cf77e79e1f1534d97220a14d684095f7b92a
URL: https://github.com/llvm/llvm-project/commit/8f18cf77e79e1f1534d97220a14d684095f7b92a
DIFF: https://github.com/llvm/llvm-project/commit/8f18cf77e79e1f1534d97220a14d684095f7b92a.diff
LOG: AMDGPU: Check for implicit defs before constant folding instruction
Can't delete the constant folded instruction if scc is used.
Fixes #63986
https://reviews.llvm.org/D157504
Added:
llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
Modified:
llvm/include/llvm/CodeGen/MachineInstr.h
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 2e1f7feb6e9c0f..2b92e4bfde3555 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1745,6 +1745,9 @@ class MachineInstr
/// Return true if all the defs of this instruction are dead.
bool allDefsAreDead() const;
+ /// Return true if all the implicit defs of this instruction are dead.
+ bool allImplicitDefsAreDead() const;
+
/// Return a valid size if the instruction is a spill instruction.
std::optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 0c4353fbc3404a..13673fbeec5851 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1497,6 +1497,16 @@ bool MachineInstr::allDefsAreDead() const {
return true;
}
+bool MachineInstr::allImplicitDefsAreDead() const {
+ for (const MachineOperand &MO : implicit_operands()) {
+ if (!MO.isReg() || MO.isUse())
+ continue;
+ if (!MO.isDead())
+ return false;
+ }
+ return true;
+}
+
/// copyImplicitOps - Copy implicit register operands from specified
/// instruction to this instruction.
void MachineInstr::copyImplicitOps(MachineFunction &MF,
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 9f1d6038f1b6d7..3adaa092aaefc4 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1035,6 +1035,9 @@ SIFoldOperands::getImmOrMaterializedImm(MachineOperand &Op) const {
// selection.
// TODO: See if a frame index with a fixed offset can fold.
bool SIFoldOperands::tryConstantFoldOp(MachineInstr *MI) const {
+ if (!MI->allImplicitDefsAreDead())
+ return false;
+
unsigned Opc = MI->getOpcode();
int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
index c347860570ba80..3db2b6ed9ab4ba 100644
--- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
@@ -790,3 +790,139 @@ body: |
S_ENDPGM 0, implicit %4
...
+
+---
+name: constant_s_and_b32_only_implicit_def_scc_is_used
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_s_and_b32_only_implicit_def_scc_is_used
+ ; GCN: [[S_AND_B32_:%[0-9]+]]:sgpr_32 = S_AND_B32 32, 15, implicit-def $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit $scc
+ %0:sgpr_32 = S_MOV_B32 32
+ %1:sgpr_32 = S_MOV_B32 15
+ %2:sgpr_32 = S_AND_B32 %0, %1, implicit-def $scc
+ S_ENDPGM 0, implicit $scc
+
+...
+
+---
+name: constant_s_and_b32_implicit_def_scc_is_used
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_s_and_b32_implicit_def_scc_is_used
+ ; GCN: [[S_AND_B32_:%[0-9]+]]:sgpr_32 = S_AND_B32 32, 15, implicit-def $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]], implicit $scc
+ %0:sgpr_32 = S_MOV_B32 32
+ %1:sgpr_32 = S_MOV_B32 15
+ %2:sgpr_32 = S_AND_B32 %0, %1, implicit-def $scc
+ S_ENDPGM 0, implicit %2, implicit $scc
+
+...
+
+---
+name: constant_s_and_b32_only_implicit_def_scc_is_dead
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_s_and_b32_only_implicit_def_scc_is_dead
+ ; GCN: S_ENDPGM 0, implicit undef $scc
+ %0:sgpr_32 = S_MOV_B32 32
+ %1:sgpr_32 = S_MOV_B32 15
+ %2:sgpr_32 = S_AND_B32 %0, %1, implicit-def dead $scc
+ S_ENDPGM 0, implicit undef $scc
+
+...
+
+---
+name: constant_s_or_b32_only_implicit_def_scc_is_used
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_s_or_b32_only_implicit_def_scc_is_used
+ ; GCN: [[S_OR_B32_:%[0-9]+]]:sgpr_32 = S_OR_B32 32, 15, implicit-def $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit $scc
+ %0:sgpr_32 = S_MOV_B32 32
+ %1:sgpr_32 = S_MOV_B32 15
+ %2:sgpr_32 = S_OR_B32 %0, %1, implicit-def $scc
+ S_ENDPGM 0, implicit $scc
+
+...
+
+---
+name: constant_s_xor_b32_only_implicit_def_scc_is_used
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_s_xor_b32_only_implicit_def_scc_is_used
+ ; GCN: [[S_XOR_B32_:%[0-9]+]]:sgpr_32 = S_XOR_B32 32, 15, implicit-def $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit $scc
+ %0:sgpr_32 = S_MOV_B32 32
+ %1:sgpr_32 = S_MOV_B32 15
+ %2:sgpr_32 = S_XOR_B32 %0, %1, implicit-def $scc
+ S_ENDPGM 0, implicit $scc
+
+...
+
+---
+name: constant_s_not_b32_only_implicit_def_scc_is_used
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_s_not_b32_only_implicit_def_scc_is_used
+ ; GCN: [[S_NOT_B32_:%[0-9]+]]:sgpr_32 = S_NOT_B32 32, implicit-def $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit $scc
+ %0:sgpr_32 = S_MOV_B32 32
+ %1:sgpr_32 = S_NOT_B32 %0, implicit-def $scc
+ S_ENDPGM 0, implicit $scc
+
+...
+
+# Really really implicit operand
+---
+name: constant_v_and_b32_implicit_def_scc_is_used
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_v_and_b32_implicit_def_scc_is_used
+ ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15, implicit $exec
+ ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 32, [[V_MOV_B32_e32_]], implicit $exec, implicit-def $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit $scc
+ %0:vgpr_32 = V_MOV_B32_e32 32, implicit $exec
+ %1:vgpr_32 = V_MOV_B32_e32 15, implicit $exec
+ %2:vgpr_32 = V_AND_B32_e32 %0, %1, implicit $exec, implicit-def $scc
+ S_ENDPGM 0, implicit $scc
+
+...
+
+---
+name: constant_v_and_b32_implicit_def_vreg_is_used
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_v_and_b32_implicit_def_vreg_is_used
+ ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15, implicit $exec
+ ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 32, [[V_MOV_B32_e32_]], implicit $exec, implicit-def %3
+ ; GCN-NEXT: S_ENDPGM 0, implicit %3
+ %0:vgpr_32 = V_MOV_B32_e32 32, implicit $exec
+ %1:vgpr_32 = V_MOV_B32_e32 15, implicit $exec
+ %2:vgpr_32 = V_AND_B32_e32 %0, %1, implicit $exec, implicit-def %3:vgpr_32
+ S_ENDPGM 0, implicit %3
+
+...
+---
+name: constant_v_and_b32_implicit_use
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: constant_v_and_b32_implicit_use
+ ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
+ %0:vgpr_32 = V_MOV_B32_e32 32, implicit $exec
+ %1:vgpr_32 = V_MOV_B32_e32 15, implicit $exec
+ %2:vgpr_32 = V_MOV_B32_e32 24, implicit $exec
+ %3:vgpr_32 = V_AND_B32_e32 %0, %1, implicit $exec, implicit %2:vgpr_32
+ S_ENDPGM 0, implicit %3
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll b/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
new file mode 100644
index 00000000000000..0e6c1aecb6774a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
@@ -0,0 +1,319 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -O3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
+
+%"struct.__llvm_libc::rpc::Buffer" = type { [8 x i64] }
+
+define void @issue63986(i64 %0, i64 %idxprom) {
+; CHECK-LABEL: issue63986:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], 6, v[2:3]
+; CHECK-NEXT: s_mov_b64 s[4:5], 0
+; CHECK-NEXT: ; %bb.1: ; %loop-memcpy-expansion.preheader
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], 6, v[2:3]
+; CHECK-NEXT: s_mov_b64 s[6:7], 0
+; CHECK-NEXT: .LBB0_2: ; %loop-memcpy-expansion
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: v_mov_b32_e32 v9, s7
+; CHECK-NEXT: v_mov_b32_e32 v8, s6
+; CHECK-NEXT: flat_load_ubyte v10, v[8:9] offset:5
+; CHECK-NEXT: flat_load_ubyte v11, v[8:9] offset:6
+; CHECK-NEXT: flat_load_ubyte v12, v[8:9] offset:7
+; CHECK-NEXT: flat_load_ubyte v13, v[8:9] offset:3
+; CHECK-NEXT: flat_load_ubyte v14, v[8:9] offset:2
+; CHECK-NEXT: flat_load_ubyte v15, v[8:9] offset:1
+; CHECK-NEXT: flat_load_ubyte v16, v[8:9]
+; CHECK-NEXT: flat_load_ubyte v17, v[8:9] offset:4
+; CHECK-NEXT: flat_load_ubyte v18, v[8:9] offset:13
+; CHECK-NEXT: flat_load_ubyte v19, v[8:9] offset:14
+; CHECK-NEXT: flat_load_ubyte v20, v[8:9] offset:15
+; CHECK-NEXT: flat_load_ubyte v21, v[8:9] offset:11
+; CHECK-NEXT: flat_load_ubyte v22, v[8:9] offset:10
+; CHECK-NEXT: flat_load_ubyte v23, v[8:9] offset:9
+; CHECK-NEXT: flat_load_ubyte v24, v[8:9] offset:8
+; CHECK-NEXT: flat_load_ubyte v25, v[8:9] offset:12
+; CHECK-NEXT: s_add_u32 s4, s4, 1
+; CHECK-NEXT: s_addc_u32 s5, s5, 0
+; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, s6, v6
+; CHECK-NEXT: v_cmp_ge_u64_e64 s[8:9], s[4:5], 2
+; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v7, vcc
+; CHECK-NEXT: s_add_u32 s6, s6, 16
+; CHECK-NEXT: s_addc_u32 s7, s7, 0
+; CHECK-NEXT: s_and_b64 vcc, exec, s[8:9]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_store_byte v[8:9], v13 offset:3
+; CHECK-NEXT: flat_store_byte v[8:9], v14 offset:2
+; CHECK-NEXT: flat_store_byte v[8:9], v15 offset:1
+; CHECK-NEXT: flat_store_byte v[8:9], v16
+; CHECK-NEXT: flat_store_byte v[8:9], v12 offset:7
+; CHECK-NEXT: flat_store_byte v[8:9], v11 offset:6
+; CHECK-NEXT: flat_store_byte v[8:9], v10 offset:5
+; CHECK-NEXT: flat_store_byte v[8:9], v17 offset:4
+; CHECK-NEXT: flat_store_byte v[8:9], v21 offset:11
+; CHECK-NEXT: flat_store_byte v[8:9], v22 offset:10
+; CHECK-NEXT: flat_store_byte v[8:9], v23 offset:9
+; CHECK-NEXT: flat_store_byte v[8:9], v24 offset:8
+; CHECK-NEXT: flat_store_byte v[8:9], v20 offset:15
+; CHECK-NEXT: flat_store_byte v[8:9], v19 offset:14
+; CHECK-NEXT: flat_store_byte v[8:9], v18 offset:13
+; CHECK-NEXT: flat_store_byte v[8:9], v25 offset:12
+; CHECK-NEXT: s_cbranch_vccz .LBB0_2
+; CHECK-NEXT: ; %bb.3: ; %loop-memcpy-residual-header
+; CHECK-NEXT: s_and_b32 s4, 32, 15
+; CHECK-NEXT: s_mov_b32 s5, 0
+; CHECK-NEXT: s_cbranch_scc0 .LBB0_5
+; CHECK-NEXT: ; %bb.4:
+; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
+; CHECK-NEXT: s_branch .LBB0_6
+; CHECK-NEXT: .LBB0_5: ; %loop-memcpy-residual-header.post-loop-memcpy-expansion_crit_edge
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], 6, v[2:3]
+; CHECK-NEXT: s_cbranch_execnz .LBB0_9
+; CHECK-NEXT: .LBB0_6: ; %loop-memcpy-residual.preheader
+; CHECK-NEXT: v_or_b32_e32 v2, 32, v4
+; CHECK-NEXT: v_mov_b32_e32 v3, v5
+; CHECK-NEXT: s_mov_b64 s[6:7], 0
+; CHECK-NEXT: .LBB0_7: ; %loop-memcpy-residual
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: s_add_u32 s8, 32, s6
+; CHECK-NEXT: s_addc_u32 s9, 0, s7
+; CHECK-NEXT: v_mov_b32_e32 v6, s8
+; CHECK-NEXT: v_mov_b32_e32 v7, s9
+; CHECK-NEXT: flat_load_ubyte v10, v[6:7]
+; CHECK-NEXT: v_mov_b32_e32 v9, s7
+; CHECK-NEXT: v_mov_b32_e32 v7, s5
+; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, s6, v2
+; CHECK-NEXT: s_add_u32 s6, s6, 1
+; CHECK-NEXT: v_mov_b32_e32 v6, s4
+; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, v3, v9, vcc
+; CHECK-NEXT: s_addc_u32 s7, s7, 0
+; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[6:7]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_store_byte v[8:9], v10
+; CHECK-NEXT: s_cbranch_vccnz .LBB0_7
+; CHECK-NEXT: ; %bb.8:
+; CHECK-NEXT: v_mov_b32_e32 v2, v4
+; CHECK-NEXT: v_mov_b32_e32 v3, v5
+; CHECK-NEXT: .LBB0_9: ; %post-loop-memcpy-expansion
+; CHECK-NEXT: v_lshrrev_b64 v[4:5], 4, v[0:1]
+; CHECK-NEXT: v_and_b32_e32 v6, 15, v0
+; CHECK-NEXT: v_mov_b32_e32 v7, 0
+; CHECK-NEXT: v_and_b32_e32 v0, -16, v0
+; CHECK-NEXT: v_cmp_ne_u64_e64 s[4:5], 0, v[4:5]
+; CHECK-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[6:7]
+; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, v2, v0
+; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, v3, v1, vcc
+; CHECK-NEXT: s_branch .LBB0_12
+; CHECK-NEXT: .LBB0_10: ; %Flow19
+; CHECK-NEXT: ; in Loop: Header=BB0_12 Depth=1
+; CHECK-NEXT: s_or_b64 exec, exec, s[10:11]
+; CHECK-NEXT: s_mov_b64 s[8:9], 0
+; CHECK-NEXT: .LBB0_11: ; %Flow21
+; CHECK-NEXT: ; in Loop: Header=BB0_12 Depth=1
+; CHECK-NEXT: s_andn2_b64 vcc, exec, s[8:9]
+; CHECK-NEXT: s_cbranch_vccz .LBB0_20
+; CHECK-NEXT: .LBB0_12: ; %while.cond
+; CHECK-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NEXT: ; Child Loop BB0_14 Depth 2
+; CHECK-NEXT: ; Child Loop BB0_18 Depth 2
+; CHECK-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
+; CHECK-NEXT: s_cbranch_execz .LBB0_15
+; CHECK-NEXT: ; %bb.13: ; %loop-memcpy-expansion2.preheader
+; CHECK-NEXT: ; in Loop: Header=BB0_12 Depth=1
+; CHECK-NEXT: s_mov_b64 s[10:11], 0
+; CHECK-NEXT: s_mov_b64 s[12:13], 0
+; CHECK-NEXT: s_mov_b64 s[14:15], 0
+; CHECK-NEXT: .LBB0_14: ; %loop-memcpy-expansion2
+; CHECK-NEXT: ; Parent Loop BB0_12 Depth=1
+; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NEXT: v_mov_b32_e32 v10, s10
+; CHECK-NEXT: v_mov_b32_e32 v11, s11
+; CHECK-NEXT: flat_load_ubyte v12, v[10:11] offset:5
+; CHECK-NEXT: flat_load_ubyte v13, v[10:11] offset:6
+; CHECK-NEXT: flat_load_ubyte v14, v[10:11] offset:7
+; CHECK-NEXT: flat_load_ubyte v15, v[10:11] offset:3
+; CHECK-NEXT: flat_load_ubyte v16, v[10:11] offset:2
+; CHECK-NEXT: flat_load_ubyte v17, v[10:11] offset:1
+; CHECK-NEXT: flat_load_ubyte v18, v[10:11]
+; CHECK-NEXT: flat_load_ubyte v19, v[10:11] offset:4
+; CHECK-NEXT: flat_load_ubyte v20, v[10:11] offset:13
+; CHECK-NEXT: flat_load_ubyte v21, v[10:11] offset:14
+; CHECK-NEXT: flat_load_ubyte v22, v[10:11] offset:15
+; CHECK-NEXT: flat_load_ubyte v23, v[10:11] offset:11
+; CHECK-NEXT: flat_load_ubyte v24, v[10:11] offset:10
+; CHECK-NEXT: flat_load_ubyte v25, v[10:11] offset:9
+; CHECK-NEXT: flat_load_ubyte v26, v[10:11] offset:8
+; CHECK-NEXT: flat_load_ubyte v27, v[10:11] offset:12
+; CHECK-NEXT: s_add_u32 s14, s14, 1
+; CHECK-NEXT: v_add_co_u32_e32 v10, vcc, s10, v2
+; CHECK-NEXT: v_addc_co_u32_e32 v11, vcc, v11, v3, vcc
+; CHECK-NEXT: s_addc_u32 s15, s15, 0
+; CHECK-NEXT: s_add_u32 s10, s10, 16
+; CHECK-NEXT: v_cmp_ge_u64_e32 vcc, s[14:15], v[4:5]
+; CHECK-NEXT: s_addc_u32 s11, s11, 0
+; CHECK-NEXT: s_or_b64 s[12:13], vcc, s[12:13]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_store_byte v[10:11], v15 offset:3
+; CHECK-NEXT: flat_store_byte v[10:11], v16 offset:2
+; CHECK-NEXT: flat_store_byte v[10:11], v17 offset:1
+; CHECK-NEXT: flat_store_byte v[10:11], v18
+; CHECK-NEXT: flat_store_byte v[10:11], v14 offset:7
+; CHECK-NEXT: flat_store_byte v[10:11], v13 offset:6
+; CHECK-NEXT: flat_store_byte v[10:11], v12 offset:5
+; CHECK-NEXT: flat_store_byte v[10:11], v19 offset:4
+; CHECK-NEXT: flat_store_byte v[10:11], v23 offset:11
+; CHECK-NEXT: flat_store_byte v[10:11], v24 offset:10
+; CHECK-NEXT: flat_store_byte v[10:11], v25 offset:9
+; CHECK-NEXT: flat_store_byte v[10:11], v26 offset:8
+; CHECK-NEXT: flat_store_byte v[10:11], v22 offset:15
+; CHECK-NEXT: flat_store_byte v[10:11], v21 offset:14
+; CHECK-NEXT: flat_store_byte v[10:11], v20 offset:13
+; CHECK-NEXT: flat_store_byte v[10:11], v27 offset:12
+; CHECK-NEXT: s_andn2_b64 exec, exec, s[12:13]
+; CHECK-NEXT: s_cbranch_execnz .LBB0_14
+; CHECK-NEXT: .LBB0_15: ; %Flow20
+; CHECK-NEXT: ; in Loop: Header=BB0_12 Depth=1
+; CHECK-NEXT: s_or_b64 exec, exec, s[8:9]
+; CHECK-NEXT: s_mov_b64 s[8:9], -1
+; CHECK-NEXT: s_cbranch_execz .LBB0_11
+; CHECK-NEXT: ; %bb.16: ; %loop-memcpy-residual-header5
+; CHECK-NEXT: ; in Loop: Header=BB0_12 Depth=1
+; CHECK-NEXT: s_and_saveexec_b64 s[8:9], s[6:7]
+; CHECK-NEXT: s_xor_b64 s[10:11], exec, s[8:9]
+; CHECK-NEXT: s_cbranch_execz .LBB0_10
+; CHECK-NEXT: ; %bb.17: ; %loop-memcpy-residual4.preheader
+; CHECK-NEXT: ; in Loop: Header=BB0_12 Depth=1
+; CHECK-NEXT: s_mov_b64 s[12:13], 0
+; CHECK-NEXT: s_mov_b64 s[14:15], 0
+; CHECK-NEXT: .LBB0_18: ; %loop-memcpy-residual4
+; CHECK-NEXT: ; Parent Loop BB0_12 Depth=1
+; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NEXT: v_mov_b32_e32 v12, s15
+; CHECK-NEXT: v_add_co_u32_e32 v10, vcc, s14, v0
+; CHECK-NEXT: v_addc_co_u32_e32 v11, vcc, v1, v12, vcc
+; CHECK-NEXT: flat_load_ubyte v13, v[10:11]
+; CHECK-NEXT: v_add_co_u32_e32 v10, vcc, s14, v8
+; CHECK-NEXT: s_add_u32 s14, s14, 1
+; CHECK-NEXT: s_addc_u32 s15, s15, 0
+; CHECK-NEXT: v_cmp_ge_u64_e64 s[8:9], s[14:15], v[6:7]
+; CHECK-NEXT: v_addc_co_u32_e32 v11, vcc, v9, v12, vcc
+; CHECK-NEXT: s_or_b64 s[12:13], s[8:9], s[12:13]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_store_byte v[10:11], v13
+; CHECK-NEXT: s_andn2_b64 exec, exec, s[12:13]
+; CHECK-NEXT: s_cbranch_execnz .LBB0_18
+; CHECK-NEXT: ; %bb.19: ; %Flow
+; CHECK-NEXT: ; in Loop: Header=BB0_12 Depth=1
+; CHECK-NEXT: s_or_b64 exec, exec, s[12:13]
+; CHECK-NEXT: s_branch .LBB0_10
+; CHECK-NEXT: .LBB0_20: ; %DummyReturnBlock
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %arrayidx = getelementptr [32 x %"struct.__llvm_libc::rpc::Buffer"], ptr null, i64 0, i64 %idxprom
+ %spec.select = tail call i64 @llvm.umin.i64(i64 sub (i64 ptrtoint (ptr addrspacecast (ptr addrspace(4) inttoptr (i64 32 to ptr addrspace(4)) to ptr) to i64), i64 ptrtoint (ptr addrspacecast (ptr addrspace(4) null to ptr) to i64)), i64 56)
+ tail call void @llvm.memcpy.p0.p0.i64(ptr %arrayidx, ptr null, i64 %spec.select, i1 false)
+ br label %while.cond
+
+while.cond: ; preds = %while.cond
+ tail call void @llvm.memcpy.p0.p0.i64(ptr %arrayidx, ptr null, i64 %0, i1 false)
+ br label %while.cond
+}
+
+define void @issue63986_reduced_expanded(i64 %idxprom) {
+; CHECK-LABEL: issue63986_reduced_expanded:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: ; %bb.1: ; %loop-memcpy-expansion.preheader
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+; CHECK-NEXT: ; %bb.2: ; %loop-memcpy-residual-header
+; CHECK-NEXT: s_and_b32 s4, 32, 15
+; CHECK-NEXT: s_mov_b32 s5, 0
+; CHECK-NEXT: s_cbranch_scc0 .LBB1_4
+; CHECK-NEXT: ; %bb.3:
+; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
+; CHECK-NEXT: s_branch .LBB1_5
+; CHECK-NEXT: .LBB1_4: ; %loop-memcpy-residual-header.post-loop-memcpy-expansion_crit_edge
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; CHECK-NEXT: s_cbranch_execnz .LBB1_8
+; CHECK-NEXT: .LBB1_5: ; %loop-memcpy-residual.preheader
+; CHECK-NEXT: s_mov_b64 s[6:7], 0
+; CHECK-NEXT: .LBB1_6: ; %loop-memcpy-residual
+; CHECK-NEXT: s_add_u32 s6, s6, 1
+; CHECK-NEXT: v_mov_b32_e32 v0, s4
+; CHECK-NEXT: v_mov_b32_e32 v1, s5
+; CHECK-NEXT: s_addc_u32 s7, s7, 0
+; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
+; CHECK-NEXT: s_mov_b64 s[6:7], 1
+; CHECK-NEXT: s_cbranch_vccnz .LBB1_6
+; CHECK-NEXT: ; %bb.7: ; %Flow
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: .LBB1_8: ; %post-loop-memcpy-expansion
+; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: s_and_b64 vcc, exec, 0
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:3
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:2
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:1
+; CHECK-NEXT: flat_store_byte v[0:1], v2
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:7
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:6
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:5
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:4
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:11
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:10
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:9
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:8
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:15
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:14
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:13
+; CHECK-NEXT: flat_store_byte v[0:1], v2 offset:12
+; CHECK-NEXT: .LBB1_9: ; %loop-memcpy-expansion2
+; CHECK-NEXT: s_mov_b64 vcc, vcc
+; CHECK-NEXT: s_cbranch_vccz .LBB1_9
+; CHECK-NEXT: ; %bb.10: ; %DummyReturnBlock
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %spec.select = tail call i64 @llvm.umin.i64(i64 sub (i64 ptrtoint (ptr addrspacecast (ptr addrspace(4) inttoptr (i64 32 to ptr addrspace(4)) to ptr) to i64), i64 ptrtoint (ptr addrspacecast (ptr addrspace(4) null to ptr) to i64)), i64 56)
+ %i = trunc i64 %spec.select to i32
+ %i1 = urem i32 %i, 16
+ %i2 = zext i32 %i to i64
+ %i3 = zext i32 %i1 to i64
+ %i4 = icmp ne i64 %i2, 0
+ br i1 %i4, label %loop-memcpy-expansion.preheader, label %loop-memcpy-residual-header
+
+loop-memcpy-expansion.preheader: ; preds = %entry
+ ret void
+
+loop-memcpy-residual: ; preds = %loop-memcpy-residual.preheader, %loop-memcpy-residual
+ %residual-loop-index1 = phi i64 [ 1, %loop-memcpy-residual ], [ 0, %loop-memcpy-residual.preheader ]
+ %i5 = add i64 %residual-loop-index1, 1
+ %i6 = icmp ult i64 %i5, %i3
+ br i1 %i6, label %loop-memcpy-residual, label %post-loop-memcpy-expansion
+
+post-loop-memcpy-expansion: ; preds = %loop-memcpy-residual-header.post-loop-memcpy-expansion_crit_edge, %loop-memcpy-residual
+ %.pre-phi = phi i64 [ %.pre, %loop-memcpy-residual-header.post-loop-memcpy-expansion_crit_edge ], [ 0, %loop-memcpy-residual ]
+ br label %loop-memcpy-expansion2
+
+loop-memcpy-expansion2: ; preds = %loop-memcpy-expansion2, %post-loop-memcpy-expansion
+ %scevgep7 = getelementptr i8, ptr null, i64 %.pre-phi
+ store <4 x i32> zeroinitializer, ptr %scevgep7, align 1
+ br label %loop-memcpy-expansion2
+
+loop-memcpy-residual-header: ; preds = %entry
+ %i7 = icmp ne i64 %i3, 0
+ br i1 %i7, label %loop-memcpy-residual.preheader, label %loop-memcpy-residual-header.post-loop-memcpy-expansion_crit_edge
+
+loop-memcpy-residual-header.post-loop-memcpy-expansion_crit_edge: ; preds = %loop-memcpy-residual-header
+ %.pre = shl i64 %idxprom, 1
+ br label %post-loop-memcpy-expansion
+
+loop-memcpy-residual.preheader: ; preds = %loop-memcpy-residual-header
+ br label %loop-memcpy-residual
+}
+
+declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #0
+declare i64 @llvm.umin.i64(i64, i64) #1
+
+attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
+attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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