[llvm] d11b44e - [AMDGPU] Add some GFX11 MCA test coverage
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 11 05:49:15 PDT 2023
Author: Jay Foad
Date: 2023-08-11T13:48:59+01:00
New Revision: d11b44eca99509bcf6e85b880854082b04cefdd7
URL: https://github.com/llvm/llvm-project/commit/d11b44eca99509bcf6e85b880854082b04cefdd7
DIFF: https://github.com/llvm/llvm-project/commit/d11b44eca99509bcf6e85b880854082b04cefdd7.diff
LOG: [AMDGPU] Add some GFX11 MCA test coverage
Added:
Modified:
llvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s
Removed:
################################################################################
diff --git a/llvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s b/llvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s
index 359008d04ddc90..64cf577e031a3f 100644
--- a/llvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s
+++ b/llvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s -check-prefixes=CHECK,GFX10
+# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1100 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s -check-prefixes=CHECK,GFX11
v_log_f32 v0, v0
v_rcp_f32 v0, v0
@@ -11,12 +12,20 @@ v_sqrt_f64 v[2:3], v[0:1]
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 7
-# CHECK-NEXT: Total Cycles: 94
+
+# GFX10-NEXT: Total Cycles: 94
+# GFX11-NEXT: Total Cycles: 142
+
# CHECK-NEXT: Total uOps: 7
# CHECK: Dispatch Width: 1
-# CHECK-NEXT: uOps Per Cycle: 0.07
-# CHECK-NEXT: IPC: 0.07
+
+# GFX10-NEXT: uOps Per Cycle: 0.07
+# GFX10-NEXT: IPC: 0.07
+
+# GFX11-NEXT: uOps Per Cycle: 0.05
+# GFX11-NEXT: IPC: 0.05
+
# CHECK-NEXT: Block RThroughput: 7.0
# CHECK: Instruction Info:
@@ -32,45 +41,85 @@ v_sqrt_f64 v[2:3], v[0:1]
# CHECK-NEXT: 1 10 1.00 U v_rcp_f32_e32 v0, v0
# CHECK-NEXT: 1 10 1.00 U v_rsq_f32_e32 v1, v1
# CHECK-NEXT: 1 10 1.00 U v_sqrt_f32_e32 v2, v0
-# CHECK-NEXT: 1 24 1.00 U v_rcp_f64_e32 v[0:1], v[0:1]
-# CHECK-NEXT: 1 24 1.00 U v_rsq_f64_e32 v[1:2], v[1:2]
-# CHECK-NEXT: 1 24 1.00 U v_sqrt_f64_e32 v[2:3], v[0:1]
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - HWBranch
-# CHECK-NEXT: [1] - HWExport
-# CHECK-NEXT: [2] - HWLGKM
-# CHECK-NEXT: [3] - HWRC
-# CHECK-NEXT: [4] - HWSALU
-# CHECK-NEXT: [5] - HWTransVALU
-# CHECK-NEXT: [6] - HWVALU
-# CHECK-NEXT: [7] - HWVMEM
+
+# GFX10-NEXT: 1 24 1.00 U v_rcp_f64_e32 v[0:1], v[0:1]
+# GFX10-NEXT: 1 24 1.00 U v_rsq_f64_e32 v[1:2], v[1:2]
+# GFX10-NEXT: 1 24 1.00 U v_sqrt_f64_e32 v[2:3], v[0:1]
+
+# GFX11-NEXT: 1 40 1.00 U v_rcp_f64_e32 v[0:1], v[0:1]
+# GFX11-NEXT: 1 40 1.00 U v_rsq_f64_e32 v[1:2], v[1:2]
+# GFX11-NEXT: 1 40 1.00 U v_sqrt_f64_e32 v[2:3], v[0:1]
+
+# GFX10: Resources:
+# GFX10-NEXT: [0] - HWBranch
+# GFX10-NEXT: [1] - HWExport
+# GFX10-NEXT: [2] - HWLGKM
+# GFX10-NEXT: [3] - HWRC
+# GFX10-NEXT: [4] - HWSALU
+# GFX10-NEXT: [5] - HWTransVALU
+# GFX10-NEXT: [6] - HWVALU
+# GFX10-NEXT: [7] - HWVMEM
+
+# GFX11: Resources:
+# GFX11-NEXT: [0] - HWBranch
+# GFX11-NEXT: [1] - HWExport
+# GFX11-NEXT: [2] - HWLGKM
+# GFX11-NEXT: [3] - HWRC
+# GFX11-NEXT: [4] - HWSALU
+# GFX11-NEXT: [5] - HWVALU
+# GFX11-NEXT: [6] - HWVMEM
# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - - 7.00 - 7.00 3.00 -
+
+# GFX10-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# GFX10-NEXT: - - - 7.00 - 7.00 3.00 -
+
+# GFX11-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# GFX11-NEXT: - - - 7.00 - 7.00 -
# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - - 1.00 - 1.00 - - v_log_f32_e32 v0, v0
-# CHECK-NEXT: - - - 1.00 - 1.00 - - v_rcp_f32_e32 v0, v0
-# CHECK-NEXT: - - - 1.00 - 1.00 - - v_rsq_f32_e32 v1, v1
-# CHECK-NEXT: - - - 1.00 - 1.00 - - v_sqrt_f32_e32 v2, v0
-# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1]
-# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[1:2], v[1:2]
-# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[2:3], v[0:1]
+
+# GFX10-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# GFX10-NEXT: - - - 1.00 - 1.00 - - v_log_f32_e32 v0, v0
+# GFX10-NEXT: - - - 1.00 - 1.00 - - v_rcp_f32_e32 v0, v0
+# GFX10-NEXT: - - - 1.00 - 1.00 - - v_rsq_f32_e32 v1, v1
+# GFX10-NEXT: - - - 1.00 - 1.00 - - v_sqrt_f32_e32 v2, v0
+# GFX10-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1]
+# GFX10-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[1:2], v[1:2]
+# GFX10-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[2:3], v[0:1]
+
+# GFX11-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# GFX11-NEXT: - - - 1.00 - 1.00 - v_log_f32_e32 v0, v0
+# GFX11-NEXT: - - - 1.00 - 1.00 - v_rcp_f32_e32 v0, v0
+# GFX11-NEXT: - - - 1.00 - 1.00 - v_rsq_f32_e32 v1, v1
+# GFX11-NEXT: - - - 1.00 - 1.00 - v_sqrt_f32_e32 v2, v0
+# GFX11-NEXT: - - - 1.00 - 1.00 - v_rcp_f64_e32 v[0:1], v[0:1]
+# GFX11-NEXT: - - - 1.00 - 1.00 - v_rsq_f64_e32 v[1:2], v[1:2]
+# GFX11-NEXT: - - - 1.00 - 1.00 - v_sqrt_f64_e32 v[2:3], v[0:1]
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123
-# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789
-
-# CHECK: [0,0] DeeeeeeeeeE . . . . . . . . . . . . . . . . . v_log_f32_e32 v0, v0
-# CHECK-NEXT: [0,1] . . DeeeeeeeeeE . . . . . . . . . . . . . . . v_rcp_f32_e32 v0, v0
-# CHECK-NEXT: [0,2] . . .DeeeeeeeeeE . . . . . . . . . . . . . . . v_rsq_f32_e32 v1, v1
-# CHECK-NEXT: [0,3] . . . . DeeeeeeeeeE . . . . . . . . . . . . . v_sqrt_f32_e32 v2, v0
-# CHECK-NEXT: [0,4] . . . . .DeeeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_rcp_f64_e32 v[0:1], v[0:1]
-# CHECK-NEXT: [0,5] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE. . . . . . v_rsq_f64_e32 v[1:2], v[1:2]
-# CHECK-NEXT: [0,6] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[2:3], v[0:1]
+
+# GFX10-NEXT: 0123456789 0123456789 0123456789 0123456789 0123
+# GFX10-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789
+
+# GFX11-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789
+# GFX11-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 01
+
+# GFX10: [0,0] DeeeeeeeeeE . . . . . . . . . . . . . . . . . v_log_f32_e32 v0, v0
+# GFX10-NEXT: [0,1] . . DeeeeeeeeeE . . . . . . . . . . . . . . . v_rcp_f32_e32 v0, v0
+# GFX10-NEXT: [0,2] . . .DeeeeeeeeeE . . . . . . . . . . . . . . . v_rsq_f32_e32 v1, v1
+# GFX10-NEXT: [0,3] . . . . DeeeeeeeeeE . . . . . . . . . . . . . v_sqrt_f32_e32 v2, v0
+# GFX10-NEXT: [0,4] . . . . .DeeeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_rcp_f64_e32 v[0:1], v[0:1]
+# GFX10-NEXT: [0,5] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE. . . . . . v_rsq_f64_e32 v[1:2], v[1:2]
+# GFX10-NEXT: [0,6] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[2:3], v[0:1]
+
+# GFX11: [0,0] DeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . .. v_log_f32_e32 v0, v0
+# GFX11-NEXT: [0,1] . . DeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . .. v_rcp_f32_e32 v0, v0
+# GFX11-NEXT: [0,2] . . .DeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . .. v_rsq_f32_e32 v1, v1
+# GFX11-NEXT: [0,3] . . . . DeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . .. v_sqrt_f32_e32 v2, v0
+# GFX11-NEXT: [0,4] . . . . .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . .. v_rcp_f64_e32 v[0:1], v[0:1]
+# GFX11-NEXT: [0,5] . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE . . . . . . . .. v_rsq_f64_e32 v[1:2], v[1:2]
+# GFX11-NEXT: [0,6] . . . . . . . . . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[2:3], v[0:1]
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
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