[llvm] 7720b9a - [AArch64] Extend and cleanup vecreduce.fmin/max tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 11 04:16:26 PDT 2023
Author: David Green
Date: 2023-08-11T12:16:22+01:00
New Revision: 7720b9a7e8f5252360f61e521f02364253e5c761
URL: https://github.com/llvm/llvm-project/commit/7720b9a7e8f5252360f61e521f02364253e5c761
DIFF: https://github.com/llvm/llvm-project/commit/7720b9a7e8f5252360f61e521f02364253e5c761.diff
LOG: [AArch64] Extend and cleanup vecreduce.fmin/max tests. NFC
See D156614 and D156615. This extends and uniforms the types tested in
vecreduce min/max tests to make them more useful to GlobalISel.
Added:
Modified:
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
index 8d952a443c7162..138671670b652e 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
@@ -1,14 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
declare half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
declare float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
declare double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a)
+declare half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
+declare half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a)
+declare half @llvm.vector.reduce.fmax.v16f16(<16 x half> %a)
+declare float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a)
+declare float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
+declare float @llvm.vector.reduce.fmax.v8f32(<8 x float> %a)
+declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
+declare double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
+declare double @llvm.vector.reduce.fmax.v4f64(<4 x double> %a)
+
+declare half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
-declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
define half @test_v1f16(<1 x half> %a) nounwind {
; CHECK-LABEL: test_v1f16:
@@ -44,19 +55,226 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
ret fp128 %b
}
-; TODO: This doesn't work, because ExpandReductions only supports power of two
-; unordered reductions.
-;define float @test_v3f32(<3 x float> %a) nounwind {
-; %b = call float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
-; ret float %b
-;}
+define half @test_v4f16(<4 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v4f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s2, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: mov h0, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v4f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
+; CHECK-FP-NEXT: ret
+ %b = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
+ ret half %b
+}
-define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
-; CHECK-LABEL: test_v2f128:
+define half @test_v4f16_ninf(<4 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v4f16_ninf:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s2, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: mov h0, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v4f16_ninf:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
+; CHECK-FP-NEXT: ret
+ %b = call ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
+ ret half %b
+}
+
+define half @test_v8f16(<8 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v8f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s2, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[4]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[5]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[6]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v8f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a)
+ ret half %b
+}
+
+define half @test_v16f16(<16 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v16f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h2, v1.h[1]
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s4, h1
+; CHECK-NOFP-NEXT: fcvt s5, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fmaxnm s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[2]
+; CHECK-NOFP-NEXT: fmaxnm s2, s3, s2
+; CHECK-NOFP-NEXT: mov h3, v1.h[2]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmaxnm s3, s5, s3
+; CHECK-NOFP-NEXT: mov h5, v0.h[3]
+; CHECK-NOFP-NEXT: fmaxnm s2, s4, s2
+; CHECK-NOFP-NEXT: mov h4, v1.h[3]
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmaxnm s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[4]
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-NEXT: mov h3, v1.h[4]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmaxnm s3, s5, s3
+; CHECK-NOFP-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s4
+; CHECK-NOFP-NEXT: mov h4, v1.h[5]
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmaxnm s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[6]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-NEXT: mov h3, v1.h[6]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: mov h1, v1.h[7]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmaxnm s3, s5, s3
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s4
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcvt h1, s2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v16f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
+; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %a)
+ ret half %b
+}
+
+define float @test_v2f32(<2 x float> %a) nounwind {
+; CHECK-LABEL: test_v2f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: b fmaxl
- %b = call fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
- ret fp128 %b
+; CHECK-NEXT: fmaxnmp s0, v0.2s
+; CHECK-NEXT: ret
+ %b = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a)
+ ret float %b
+}
+
+define float @test_v4f32(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
+ ret float %b
+}
+
+define float @test_v8f32(<8 x float> %a) nounwind {
+; CHECK-LABEL: test_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %a)
+ ret float %b
}
define float @test_v16f32(<16 x float> %a) nounwind {
@@ -70,3 +288,212 @@ define float @test_v16f32(<16 x float> %a) nounwind {
%b = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
ret float %b
}
+
+define double @test_v2f64(<2 x double> %a) nounwind {
+; CHECK-LABEL: test_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnmp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
+ ret double %b
+}
+
+define double @test_v4f64(<4 x double> %a) nounwind {
+; CHECK-LABEL: test_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fmaxnmp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %a)
+ ret double %b
+}
+
+define half @test_v11f16(<11 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v11f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: ldr h16, [sp, #8]
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: ldr h17, [sp]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s16, h16
+; CHECK-NOFP-NEXT: fcvt s17, h17
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s16
+; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s17
+; CHECK-NOFP-NEXT: fcvt s16, h16
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fmaxnm s1, s2, s16
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h4
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h5
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h6
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h7
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v11f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
+; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
+; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
+; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
+; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
+; CHECK-FP-NEXT: mov x8, sp
+; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
+; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
+; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
+; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-FP-NEXT: movi v1.8h, #254, lsl #8
+; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
+; CHECK-FP-NEXT: add x8, sp, #8
+; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
+; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
+; CHECK-FP-NEXT: add x8, sp, #16
+; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
+; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
+; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
+; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
+; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
+; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
+; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
+ ret half %b
+}
+
+define half @test_v11f16_ninf(<11 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v11f16_ninf:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: ldr h16, [sp, #8]
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: ldr h17, [sp]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s16, h16
+; CHECK-NOFP-NEXT: fcvt s17, h17
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s16
+; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s17
+; CHECK-NOFP-NEXT: fcvt s16, h16
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fmaxnm s1, s2, s16
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h4
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h5
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h6
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt s1, h7
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v11f16_ninf:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
+; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
+; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
+; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
+; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
+; CHECK-FP-NEXT: mov x8, sp
+; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
+; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
+; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
+; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-FP-NEXT: movi v1.8h, #254, lsl #8
+; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
+; CHECK-FP-NEXT: add x8, sp, #8
+; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
+; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
+; CHECK-FP-NEXT: add x8, sp, #16
+; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
+; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
+; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
+; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
+; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
+; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
+; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call ninf half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
+ ret half %b
+}
+
+define float @test_v3f32(<3 x float> %a) nounwind {
+; CHECK-LABEL: test_v3f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #-4194304 // =0xffc00000
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
+ ret float %b
+}
+
+define float @test_v3f32_ninf(<3 x float> %a) nounwind {
+; CHECK-LABEL: test_v3f32_ninf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #-4194304 // =0xffc00000
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call ninf float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
+ ret float %b
+}
+
+define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
+; CHECK-LABEL: test_v2f128:
+; CHECK: // %bb.0:
+; CHECK-NEXT: b fmaxl
+ %b = call fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
+ ret fp128 %b
+}
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
index 3df8749d8978c1..9302681b709db8 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
@@ -8,11 +8,18 @@ declare double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a)
declare half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
+declare half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a)
+declare half @llvm.vector.reduce.fmax.v16f16(<16 x half> %a)
+declare float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a)
+declare float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
+declare float @llvm.vector.reduce.fmax.v8f32(<8 x float> %a)
+declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
+declare double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
+declare double @llvm.vector.reduce.fmax.v4f64(<4 x double> %a)
+
declare half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
-declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
-declare double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
define half @test_v1f16(<1 x half> %a) nounwind {
; CHECK-LABEL: test_v1f16:
@@ -106,6 +113,209 @@ define half @test_v4f16_ninf(<4 x half> %a) nounwind {
ret half %b
}
+define half @test_v8f16(<8 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v8f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s2, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[4]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[5]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[6]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v8f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a)
+ ret half %b
+}
+
+define half @test_v16f16(<16 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v16f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h2, v1.h[1]
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s4, h1
+; CHECK-NOFP-NEXT: fcvt s5, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s3, s2
+; CHECK-NOFP-NEXT: fcsel s2, s3, s2, gt
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-NEXT: mov h4, v1.h[2]
+; CHECK-NOFP-NEXT: mov h5, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fmaxnm s2, s3, s2
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-NEXT: mov h4, v1.h[3]
+; CHECK-NOFP-NEXT: mov h5, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-NEXT: mov h4, v1.h[4]
+; CHECK-NOFP-NEXT: mov h5, v0.h[4]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-NEXT: mov h4, v1.h[5]
+; CHECK-NOFP-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-NEXT: mov h4, v1.h[6]
+; CHECK-NOFP-NEXT: mov h5, v0.h[6]
+; CHECK-NOFP-NEXT: mov h1, v1.h[7]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-NEXT: fcmp s0, s1
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcsel s0, s0, s1, gt
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt h1, s2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v16f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
+; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fmax.v16f16(<16 x half> %a)
+ ret half %b
+}
+
+define float @test_v2f32(<2 x float> %a) nounwind {
+; CHECK-LABEL: test_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnmp s0, v0.2s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a)
+ ret float %b
+}
+
+define float @test_v4f32(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
+ ret float %b
+}
+
+define float @test_v8f32(<8 x float> %a) nounwind {
+; CHECK-LABEL: test_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmax.v8f32(<8 x float> %a)
+ ret float %b
+}
+
+define float @test_v16f32(<16 x float> %a) nounwind {
+; CHECK-LABEL: test_v16f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
+ ret float %b
+}
+
+define double @test_v2f64(<2 x double> %a) nounwind {
+; CHECK-LABEL: test_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnmp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
+ ret double %b
+}
+
+define double @test_v4f64(<4 x double> %a) nounwind {
+; CHECK-LABEL: test_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fmaxnmp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %a)
+ ret double %b
+}
+
define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-LABEL: test_v11f16:
; CHECK-NOFP: // %bb.0:
@@ -114,7 +324,7 @@ define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-NEXT: ldr h17, [sp]
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: adrp x8, .LCPI6_0
+; CHECK-NOFP-NEXT: adrp x8, .LCPI14_0
; CHECK-NOFP-NEXT: fcvt s16, h16
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: fcvt s17, h17
@@ -131,7 +341,7 @@ define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcsel s1, s2, s16, gt
-; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI6_0]
+; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI14_0]
; CHECK-NOFP-NEXT: mov w8, #-8388608 // =0xff800000
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcvt h1, s1
@@ -221,7 +431,7 @@ define half @test_v11f16_ninf(<11 x half> %a) nounwind {
; CHECK-NOFP-NEXT: ldr h17, [sp]
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: adrp x8, .LCPI7_0
+; CHECK-NOFP-NEXT: adrp x8, .LCPI15_0
; CHECK-NOFP-NEXT: fcvt s16, h16
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: fcvt s17, h17
@@ -238,7 +448,7 @@ define half @test_v11f16_ninf(<11 x half> %a) nounwind {
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcsel s1, s2, s16, gt
-; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI7_0]
+; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI15_0]
; CHECK-NOFP-NEXT: mov w8, #57344 // =0xe000
; CHECK-NOFP-NEXT: movk w8, #51071, lsl #16
; CHECK-NOFP-NEXT: fcvt h0, s0
@@ -352,24 +562,3 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
%b = call nnan fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
ret fp128 %b
}
-
-define float @test_v16f32(<16 x float> %a) nounwind {
-; CHECK-LABEL: test_v16f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: fmaxnmv s0, v0.4s
-; CHECK-NEXT: ret
- %b = call nnan float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
- ret float %b
-}
-
-define double @test_v2f64(<2 x double> %a) nounwind {
-; CHECK-LABEL: test_v2f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmaxnmp d0, v0.2d
-; CHECK-NEXT: ret
- %b = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
- ret double %b
-}
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
index b5f3bad2cc0da4..1118a17d36946e 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
@@ -8,11 +8,18 @@ declare double @llvm.vector.reduce.fmaximum.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fmaximum.v1f128(<1 x fp128> %a)
declare half @llvm.vector.reduce.fmaximum.v4f16(<4 x half> %a)
+declare half @llvm.vector.reduce.fmaximum.v8f16(<8 x half> %a)
+declare half @llvm.vector.reduce.fmaximum.v16f16(<16 x half> %a)
+declare float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %a)
+declare float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %a)
+declare float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %a)
+declare float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %a)
+declare double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %a)
+declare double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %a)
+
declare half @llvm.vector.reduce.fmaximum.v11f16(<11 x half> %a)
declare float @llvm.vector.reduce.fmaximum.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fmaximum.v2f128(<2 x fp128> %a)
-declare float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %a)
-declare double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %a)
define half @test_v1f16(<1 x half> %a) nounwind {
; CHECK-LABEL: test_v1f16:
@@ -77,6 +84,201 @@ define half @test_v4f16(<4 x half> %a) nounwind {
ret half %b
}
+define half @test_v8f16(<8 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v8f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s2, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmax s1, s2, s1
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmax s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmax s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[4]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmax s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[5]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmax s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[6]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmax s1, s1, s2
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmax s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v8f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fmaximum.v8f16(<8 x half> %a)
+ ret half %b
+}
+
+define half @test_v16f16(<16 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v16f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h2, v1.h[1]
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s4, h1
+; CHECK-NOFP-NEXT: fcvt s5, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fmax s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[2]
+; CHECK-NOFP-NEXT: fmax s2, s3, s2
+; CHECK-NOFP-NEXT: mov h3, v1.h[2]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmax s3, s5, s3
+; CHECK-NOFP-NEXT: mov h5, v0.h[3]
+; CHECK-NOFP-NEXT: fmax s2, s4, s2
+; CHECK-NOFP-NEXT: mov h4, v1.h[3]
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmax s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[4]
+; CHECK-NOFP-NEXT: fmax s2, s2, s3
+; CHECK-NOFP-NEXT: mov h3, v1.h[4]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmax s3, s5, s3
+; CHECK-NOFP-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP-NEXT: fmax s2, s2, s4
+; CHECK-NOFP-NEXT: mov h4, v1.h[5]
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmax s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[6]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fmax s2, s2, s3
+; CHECK-NOFP-NEXT: mov h3, v1.h[6]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: mov h1, v1.h[7]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmax s3, s5, s3
+; CHECK-NOFP-NEXT: fmax s0, s0, s1
+; CHECK-NOFP-NEXT: fmax s2, s2, s4
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmax s2, s2, s3
+; CHECK-NOFP-NEXT: fcvt h1, s2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmax s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v16f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmax v0.8h, v0.8h, v1.8h
+; CHECK-FP-NEXT: fmaxv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fmaximum.v16f16(<16 x half> %a)
+ ret half %b
+}
+
+define float @test_v2f32(<2 x float> %a) nounwind {
+; CHECK-LABEL: test_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxp s0, v0.2s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %a)
+ ret float %b
+}
+
+define float @test_v4f32(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %a)
+ ret float %b
+}
+
+define float @test_v8f32(<8 x float> %a) nounwind {
+; CHECK-LABEL: test_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fmaxv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %a)
+ ret float %b
+}
+
+define float @test_v16f32(<16 x float> %a) nounwind {
+; CHECK-LABEL: test_v16f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmax v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: fmax v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: fmax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fmaxv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %a)
+ ret float %b
+}
+
+define double @test_v2f64(<2 x double> %a) nounwind {
+; CHECK-LABEL: test_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %a)
+ ret double %b
+}
+
+define double @test_v4f64(<4 x double> %a) nounwind {
+; CHECK-LABEL: test_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmax v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fmaxp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %a)
+ ret double %b
+}
+
define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-LABEL: test_v11f16:
; CHECK-NOFP: // %bb.0:
@@ -189,24 +391,3 @@ define float @test_v3f32_ninf(<3 x float> %a) nounwind {
; %b = call fp128 @llvm.vector.reduce.fmaximum.v2f128(<2 x fp128> %a)
; ret fp128 %b
;}
-
-define float @test_v16f32(<16 x float> %a) nounwind {
-; CHECK-LABEL: test_v16f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmax v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: fmax v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: fmax v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: fmaxv s0, v0.4s
-; CHECK-NEXT: ret
- %b = call float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %a)
- ret float %b
-}
-
-define double @test_v2f64(<2 x double> %a) nounwind {
-; CHECK-LABEL: test_v2f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmaxp d0, v0.2d
-; CHECK-NEXT: ret
- %b = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %a)
- ret double %b
-}
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
index 5e4205855707bc..6817047b232f1f 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
@@ -8,11 +8,18 @@ declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
declare half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
+declare half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a)
+declare half @llvm.vector.reduce.fmin.v16f16(<16 x half> %a)
+declare float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a)
+declare float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
+declare float @llvm.vector.reduce.fmin.v8f32(<8 x float> %a)
+declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
+declare double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
+declare double @llvm.vector.reduce.fmin.v4f64(<4 x double> %a)
+
declare half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
-declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
-declare double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
define half @test_v1f16(<1 x half> %a) nounwind {
; CHECK-LABEL: test_v1f16:
@@ -106,6 +113,209 @@ define half @test_v4f16_ninf(<4 x half> %a) nounwind {
ret half %b
}
+define half @test_v8f16(<8 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v8f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s2, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s1, s2, s1
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[4]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[5]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[6]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v8f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fminnmv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a)
+ ret half %b
+}
+
+define half @test_v16f16(<16 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v16f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h2, v1.h[1]
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s4, h1
+; CHECK-NOFP-NEXT: fcvt s5, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s3, s2
+; CHECK-NOFP-NEXT: fcsel s2, s3, s2, lt
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-NEXT: mov h4, v1.h[2]
+; CHECK-NOFP-NEXT: mov h5, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fminnm s2, s3, s2
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-NEXT: mov h4, v1.h[3]
+; CHECK-NOFP-NEXT: mov h5, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-NEXT: mov h4, v1.h[4]
+; CHECK-NOFP-NEXT: mov h5, v0.h[4]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-NEXT: mov h4, v1.h[5]
+; CHECK-NOFP-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-NEXT: mov h4, v1.h[6]
+; CHECK-NOFP-NEXT: mov h5, v0.h[6]
+; CHECK-NOFP-NEXT: mov h1, v1.h[7]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcmp s5, s4
+; CHECK-NOFP-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-NEXT: fcmp s0, s1
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcsel s0, s0, s1, lt
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt h1, s2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v16f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
+; CHECK-FP-NEXT: fminnmv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fmin.v16f16(<16 x half> %a)
+ ret half %b
+}
+
+define float @test_v2f32_ninf(<2 x float> %a) nounwind {
+; CHECK-LABEL: test_v2f32_ninf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnmp s0, v0.2s
+; CHECK-NEXT: ret
+ %b = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a)
+ ret float %b
+}
+
+define float @test_v4f32_ninf(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_v4f32_ninf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
+ ret float %b
+}
+
+define float @test_v8f32(<8 x float> %a) nounwind {
+; CHECK-LABEL: test_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fminnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmin.v8f32(<8 x float> %a)
+ ret float %b
+}
+
+define float @test_v16f32(<16 x float> %a) nounwind {
+; CHECK-LABEL: test_v16f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fminnmv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
+ ret float %b
+}
+
+define double @test_v2f64(<2 x double> %a) nounwind {
+; CHECK-LABEL: test_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnmp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
+ ret double %b
+}
+
+define double @test_v4f64(<4 x double> %a) nounwind {
+; CHECK-LABEL: test_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fminnmp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %a)
+ ret double %b
+}
+
define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-LABEL: test_v11f16:
; CHECK-NOFP: // %bb.0:
@@ -114,7 +324,7 @@ define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-NEXT: ldr h17, [sp]
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: adrp x8, .LCPI6_0
+; CHECK-NOFP-NEXT: adrp x8, .LCPI14_0
; CHECK-NOFP-NEXT: fcvt s16, h16
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: fcvt s17, h17
@@ -131,7 +341,7 @@ define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcsel s1, s2, s16, lt
-; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI6_0]
+; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI14_0]
; CHECK-NOFP-NEXT: mov w8, #2139095040 // =0x7f800000
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcvt h1, s1
@@ -221,7 +431,7 @@ define half @test_v11f16_ninf(<11 x half> %a) nounwind {
; CHECK-NOFP-NEXT: ldr h17, [sp]
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: adrp x8, .LCPI7_0
+; CHECK-NOFP-NEXT: adrp x8, .LCPI15_0
; CHECK-NOFP-NEXT: fcvt s16, h16
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: fcvt s17, h17
@@ -238,7 +448,7 @@ define half @test_v11f16_ninf(<11 x half> %a) nounwind {
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcsel s1, s2, s16, lt
-; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI7_0]
+; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI15_0]
; CHECK-NOFP-NEXT: mov w8, #57344 // =0xe000
; CHECK-NOFP-NEXT: movk w8, #18303, lsl #16
; CHECK-NOFP-NEXT: fcvt h0, s0
@@ -352,24 +562,3 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
%b = call nnan fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
ret fp128 %b
}
-
-define float @test_v16f32(<16 x float> %a) nounwind {
-; CHECK-LABEL: test_v16f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fminnm v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: fminnm v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: fminnmv s0, v0.4s
-; CHECK-NEXT: ret
- %b = call nnan float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
- ret float %b
-}
-
-define double @test_v2f64(<2 x double> %a) nounwind {
-; CHECK-LABEL: test_v2f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fminnmp d0, v0.2d
-; CHECK-NEXT: ret
- %b = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
- ret double %b
-}
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll b/llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
index a59696e07ff554..1fb6c32adc8819 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
@@ -8,11 +8,18 @@ declare double @llvm.vector.reduce.fminimum.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fminimum.v1f128(<1 x fp128> %a)
declare half @llvm.vector.reduce.fminimum.v4f16(<4 x half> %a)
+declare half @llvm.vector.reduce.fminimum.v8f16(<8 x half> %a)
+declare half @llvm.vector.reduce.fminimum.v16f16(<16 x half> %a)
+declare float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %a)
+declare float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %a)
+declare float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %a)
+declare float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %a)
+declare double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %a)
+declare double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %a)
+
declare half @llvm.vector.reduce.fminimum.v11f16(<11 x half> %a)
declare float @llvm.vector.reduce.fminimum.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fminimum.v2f128(<2 x fp128> %a)
-declare float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %a)
-declare double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %a)
define half @test_v1f16(<1 x half> %a) nounwind {
; CHECK-LABEL: test_v1f16:
@@ -77,6 +84,201 @@ define half @test_v4f16(<4 x half> %a) nounwind {
ret half %b
}
+define half @test_v8f16(<8 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v8f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s2, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmin s1, s2, s1
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmin s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[3]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmin s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[4]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmin s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[5]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmin s1, s1, s2
+; CHECK-NOFP-NEXT: mov h2, v0.h[6]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmin s1, s1, s2
+; CHECK-NOFP-NEXT: fcvt h1, s1
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmin s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v8f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fminv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fminimum.v8f16(<8 x half> %a)
+ ret half %b
+}
+
+define half @test_v16f16(<16 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v16f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov h2, v1.h[1]
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: fcvt s4, h1
+; CHECK-NOFP-NEXT: fcvt s5, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fmin s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[2]
+; CHECK-NOFP-NEXT: fmin s2, s3, s2
+; CHECK-NOFP-NEXT: mov h3, v1.h[2]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmin s3, s5, s3
+; CHECK-NOFP-NEXT: mov h5, v0.h[3]
+; CHECK-NOFP-NEXT: fmin s2, s4, s2
+; CHECK-NOFP-NEXT: mov h4, v1.h[3]
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmin s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[4]
+; CHECK-NOFP-NEXT: fmin s2, s2, s3
+; CHECK-NOFP-NEXT: mov h3, v1.h[4]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmin s3, s5, s3
+; CHECK-NOFP-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP-NEXT: fmin s2, s2, s4
+; CHECK-NOFP-NEXT: mov h4, v1.h[5]
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmin s4, s5, s4
+; CHECK-NOFP-NEXT: mov h5, v0.h[6]
+; CHECK-NOFP-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-NEXT: fmin s2, s2, s3
+; CHECK-NOFP-NEXT: mov h3, v1.h[6]
+; CHECK-NOFP-NEXT: fcvt h4, s4
+; CHECK-NOFP-NEXT: fcvt s5, h5
+; CHECK-NOFP-NEXT: mov h1, v1.h[7]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s4, h4
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmin s3, s5, s3
+; CHECK-NOFP-NEXT: fmin s0, s0, s1
+; CHECK-NOFP-NEXT: fmin s2, s2, s4
+; CHECK-NOFP-NEXT: fcvt h3, s3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt h2, s2
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fmin s2, s2, s3
+; CHECK-NOFP-NEXT: fcvt h1, s2
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmin s0, s1, s0
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v16f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmin v0.8h, v0.8h, v1.8h
+; CHECK-FP-NEXT: fminv h0, v0.8h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fminimum.v16f16(<16 x half> %a)
+ ret half %b
+}
+
+define float @test_v2f32(<2 x float> %a) nounwind {
+; CHECK-LABEL: test_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminp s0, v0.2s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %a)
+ ret float %b
+}
+
+define float @test_v4f32(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %a)
+ ret float %b
+}
+
+define float @test_v8f32(<8 x float> %a) nounwind {
+; CHECK-LABEL: test_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmin v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fminv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %a)
+ ret float %b
+}
+
+define float @test_v16f32(<16 x float> %a) nounwind {
+; CHECK-LABEL: test_v16f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmin v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: fmin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: fmin v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fminv s0, v0.4s
+; CHECK-NEXT: ret
+ %b = call nnan float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %a)
+ ret float %b
+}
+
+define double @test_v2f64(<2 x double> %a) nounwind {
+; CHECK-LABEL: test_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %a)
+ ret double %b
+}
+
+define double @test_v4f64(<4 x double> %a) nounwind {
+; CHECK-LABEL: test_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmin v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fminp d0, v0.2d
+; CHECK-NEXT: ret
+ %b = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %a)
+ ret double %b
+}
+
define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-LABEL: test_v11f16:
; CHECK-NOFP: // %bb.0:
@@ -189,24 +391,3 @@ define float @test_v3f32_ninf(<3 x float> %a) nounwind {
; %b = call fp128 @llvm.vector.reduce.fminimum.v2f128(<2 x fp128> %a)
; ret fp128 %b
;}
-
-define float @test_v16f32(<16 x float> %a) nounwind {
-; CHECK-LABEL: test_v16f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmin v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: fmin v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: fmin v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: fminv s0, v0.4s
-; CHECK-NEXT: ret
- %b = call float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %a)
- ret float %b
-}
-
-define double @test_v2f64(<2 x double> %a) nounwind {
-; CHECK-LABEL: test_v2f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fminp d0, v0.2d
-; CHECK-NEXT: ret
- %b = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %a)
- ret double %b
-}
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