[llvm] 2e79d0a - [X86] combineConcatVectorOps - ensure X86ISD::SHUF128 nodes use vectors with 64-bit scalars

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-08-11T11:47:18+01:00
New Revision: 2e79d0ad1c24d706fb60595bd624c1a13797a2d7

URL: https://github.com/llvm/llvm-project/commit/2e79d0ad1c24d706fb60595bd624c1a13797a2d7
DIFF: https://github.com/llvm/llvm-project/commit/2e79d0ad1c24d706fb60595bd624c1a13797a2d7.diff

LOG: [X86] combineConcatVectorOps - ensure X86ISD::SHUF128 nodes use vectors with 64-bit scalars

The actual shuffle always uses v8i64/v8f64 - the wrapping bitcast controls whether we use v16i32/v16f32 instead.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 284c2c54b7fcd4..dbe4477a7d22bf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -54603,7 +54603,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
         if ((Imm0 & 0x88) == 0 && (Imm1 & 0x88) == 0) {
           int Mask[4] = {(int)(Imm0 & 0x03), (int)((Imm0 >> 4) & 0x3), (int)(Imm1 & 0x03),
                          (int)((Imm1 >> 4) & 0x3)};
-          MVT ShuffleVT = EltSizeInBits >= 32 ? VT : MVT::v8i64;
+          MVT ShuffleVT = VT.isFloatingPoint() ? MVT::v8f64 : MVT::v8i64;
           SDValue LHS = concatSubVectors(Ops[0].getOperand(0),
                                          Ops[0].getOperand(1), DAG, DL);
           SDValue RHS = concatSubVectors(Ops[1].getOperand(0),