[PATCH] D156538: [AArch64] Try to combine FMUL with FDIV

JinGu Kang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 11 02:57:58 PDT 2023

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jaykang10 added a comment.

@dmgreen As you can see, there are some regressions.
After exact inverse for `fmul`, the `convertToInteger` sets `IsExact` to `false` in some cases.
Maybe, we could need to keep the `fdiv` patterns too...


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  https://reviews.llvm.org/D156538/new/

https://reviews.llvm.org/D156538

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