[llvm] acd17ea - [AArch64][GISel] Expand handling for G_FSQRT to more vector types
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 11 02:16:51 PDT 2023
Author: David Green
Date: 2023-08-11T10:16:45+01:00
New Revision: acd17ea662303b4f10b7bb78c5060ec67ef17ece
URL: https://github.com/llvm/llvm-project/commit/acd17ea662303b4f10b7bb78c5060ec67ef17ece
DIFF: https://github.com/llvm/llvm-project/commit/acd17ea662303b4f10b7bb78c5060ec67ef17ece.diff
LOG: [AArch64][GISel] Expand handling for G_FSQRT to more vector types
Similar to G_FABS, these can reuse the existing lowering to successfully handle
more types.
Added:
llvm/test/CodeGen/AArch64/fsqrt.ll
Modified:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir
llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
llvm/test/CodeGen/AArch64/fabs.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index afba4e185bb8ad..a4dc9d99d772b3 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4889,6 +4889,7 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
case TargetOpcode::G_FREEZE:
case TargetOpcode::G_FNEG:
case TargetOpcode::G_FABS:
+ case TargetOpcode::G_FSQRT:
case TargetOpcode::G_BSWAP:
case TargetOpcode::G_FCANONICALIZE:
case TargetOpcode::G_SEXT_INREG:
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 8124cd890dc2c8..3b4f893e650f7f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -243,8 +243,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64});
- getActionDefinitionsBuilder({G_FCEIL, G_FSQRT, G_FFLOOR, G_FRINT,
- G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND,
+ getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR, G_FRINT, G_FMA,
+ G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND,
G_FNEARBYINT, G_INTRINSIC_LRINT})
// If we don't have full FP16 support, then scalarize the elements of
// vectors containing fp16 types.
@@ -924,7 +924,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT}).lowerIf(isScalar(0));
getActionDefinitionsBuilder(
- {G_FABS, G_FMAXNUM, G_FMINNUM, G_FMAXIMUM, G_FMINIMUM})
+ {G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM, G_FMAXIMUM, G_FMINIMUM})
.legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64})
.legalIf([=](const LegalityQuery &Query) {
const auto &Ty = Query.Types[0];
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir
index ce9093b9213877..5ccb628a8a8057 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -O0 -mattr=-fullfp16 -run-pass=legalizer %s -o - | FileCheck %s
--- |
@@ -20,34 +21,21 @@ registers:
body: |
bb.1 (%ir-block.0):
liveins: $q0
- ; CHECK-LABEL: name: test_v8f16.sqrt
+ ; CHECK-LABEL: name: test_v8f16.sqrt
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
+ ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[FPEXT]]
+ ; CHECK-NEXT: [[FSQRT1:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[FPEXT1]]
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FSQRT]](<4 x s32>)
+ ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FSQRT1]](<4 x s32>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[FPTRUNC]](<4 x s16>), [[FPTRUNC1]](<4 x s16>)
+ ; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
- ; CHECK: %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<8 x s16>)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(<8 x s16>) = G_BUILD_VECTOR %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16)
%1:_(<8 x s16>) = G_FSQRT %0
$q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
@@ -63,22 +51,16 @@ registers:
body: |
bb.1 (%ir-block.0):
liveins: $d0
- ; CHECK-LABEL: name: test_v4f16.sqrt
+ ; CHECK-LABEL: name: test_v4f16.sqrt
+ ; CHECK: liveins: $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[FPEXT]]
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FSQRT]](<4 x s32>)
+ ; CHECK-NEXT: $d0 = COPY [[FPTRUNC]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
- ; CHECK: %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
- ; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
- ; CHECK: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16)
%1:_(<4 x s16>) = G_FSQRT %0
$d0 = COPY %1(<4 x s16>)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll b/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
index fd4005532e9243..eecbc4eb3f2c4b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
@@ -22,7 +22,8 @@ define %v4f16 @test_v4f16.sqrt(%v4f16 %a) {
; CHECK-FP16: fsqrt.4h
; CHECK-FP16-NEXT: ret
; GISEL-LABEL: test_v4f16.sqrt:
- ; GISEL-NOFP16-COUNT-4: fsqrt s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-NOFP16: fcvt
+ ; GISEL-NOFP16: fsqrt.4s
; GISEL-FP16-NOT: fcvt
; GISEL-FP16: fsqrt.4h
; GISEL-FP16-NEXT: ret
@@ -292,7 +293,8 @@ define %v8f16 @test_v8f16.sqrt(%v8f16 %a) {
; CHECK-FP16: fsqrt.8h
; CHECK-FP16-NEXT: ret
; GISEL-LABEL: test_v8f16.sqrt:
- ; GISEL-NOFP16-COUNT-8: fsqrt s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-NOFP16: fcvt
+ ; GISEL-NOFP16-COUNT-2: fsqrt.4s
; GISEL-FP16-NOT: fcvt
; GISEL-FP16: fsqrt.8h
; GISEL-FP16-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fabs.ll b/llvm/test/CodeGen/AArch64/fabs.ll
index 37c6ec98ce641e..8ffa20dbcecf33 100644
--- a/llvm/test/CodeGen/AArch64/fabs.ll
+++ b/llvm/test/CodeGen/AArch64/fabs.ll
@@ -160,6 +160,128 @@ entry:
ret <8 x float> %c
}
+define <7 x half> @fabs_v7f16(<7 x half> %a) {
+; CHECK-SD-NOFP16-LABEL: fabs_v7f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[2]
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h0
+; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[3]
+; CHECK-SD-NOFP16-NEXT: fcvt s1, h1
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h2
+; CHECK-SD-NOFP16-NEXT: fabs s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt s4, h4
+; CHECK-SD-NOFP16-NEXT: fabs s5, s1
+; CHECK-SD-NOFP16-NEXT: fabs s2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s3
+; CHECK-SD-NOFP16-NEXT: fabs s4, s4
+; CHECK-SD-NOFP16-NEXT: fcvt h3, s5
+; CHECK-SD-NOFP16-NEXT: mov h5, v0.h[4]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s2
+; CHECK-SD-NOFP16-NEXT: mov v1.h[1], v3.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-SD-NOFP16-NEXT: fcvt s5, h5
+; CHECK-SD-NOFP16-NEXT: mov v1.h[2], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s4
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h3
+; CHECK-SD-NOFP16-NEXT: fabs s4, s5
+; CHECK-SD-NOFP16-NEXT: mov v1.h[3], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[6]
+; CHECK-SD-NOFP16-NEXT: fabs s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s4
+; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h2
+; CHECK-SD-NOFP16-NEXT: fcvt h3, s3
+; CHECK-SD-NOFP16-NEXT: mov v1.h[4], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fabs s2, s2
+; CHECK-SD-NOFP16-NEXT: mov v1.h[5], v3.h[0]
+; CHECK-SD-NOFP16-NEXT: fabs s0, s0
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s0
+; CHECK-SD-NOFP16-NEXT: mov v1.h[6], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: mov v1.h[7], v0.h[0]
+; CHECK-SD-NOFP16-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: fabs_v7f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fabs v0.8h, v0.8h
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: fabs_v7f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov s2, v1.s[1]
+; CHECK-GI-NOFP16-NEXT: mov s3, v1.s[2]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[1], v2.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[2], v3.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[3], v0.s[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: fabs v0.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: mov s2, v1.s[1]
+; CHECK-GI-NOFP16-NEXT: mov s3, v1.s[2]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: mov v1.s[1], v2.s[0]
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[2], v3.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[3], v0.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[1]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: fabs_v7f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-FP16-NEXT: mov h6, v0.h[6]
+; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[3], v3.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[4], v4.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[5], v5.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[6], v6.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[7], v0.h[0]
+; CHECK-GI-FP16-NEXT: fabs v0.8h, v0.8h
+; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-FP16-NEXT: mov h6, v0.h[6]
+; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[3], v3.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[4], v4.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[5], v5.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[6], v6.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[7], v0.h[0]
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call <7 x half> @llvm.fabs.v7f16(<7 x half> %a)
+ ret <7 x half> %c
+}
+
define <4 x half> @fabs_v4f16(<4 x half> %a) {
; CHECK-SD-NOFP16-LABEL: fabs_v4f16:
; CHECK-SD-NOFP16: // %bb.0: // %entry
@@ -397,9 +519,9 @@ declare <3 x float> @llvm.fabs.v3f32(<3 x float>)
declare <4 x double> @llvm.fabs.v4f64(<4 x double>)
declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
+declare <7 x half> @llvm.fabs.v7f16(<7 x half>)
declare <8 x float> @llvm.fabs.v8f32(<8 x float>)
declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
declare double @llvm.fabs.f64(double)
declare float @llvm.fabs.f32(float)
declare half @llvm.fabs.f16(half)
-
diff --git a/llvm/test/CodeGen/AArch64/fsqrt.ll b/llvm/test/CodeGen/AArch64/fsqrt.ll
new file mode 100644
index 00000000000000..fc864e55a7ba76
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fsqrt.ll
@@ -0,0 +1,523 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-NOFP16
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP16
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
+
+define double @sqrt_f64(double %a) {
+; CHECK-LABEL: sqrt_f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fsqrt d0, d0
+; CHECK-NEXT: ret
+entry:
+ %c = call double @llvm.sqrt.f64(double %a)
+ ret double %c
+}
+
+define float @sqrt_f32(float %a) {
+; CHECK-LABEL: sqrt_f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fsqrt s0, s0
+; CHECK-NEXT: ret
+entry:
+ %c = call float @llvm.sqrt.f32(float %a)
+ ret float %c
+}
+
+define half @sqrt_f16(half %a) {
+; CHECK-SD-NOFP16-LABEL: sqrt_f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fsqrt s0, s0
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s0
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: sqrt_f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fsqrt h0, h0
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: sqrt_f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
+; CHECK-GI-NOFP16-NEXT: fsqrt s0, s0
+; CHECK-GI-NOFP16-NEXT: fcvt h0, s0
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: sqrt_f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: fsqrt h0, h0
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call half @llvm.sqrt.f16(half %a)
+ ret half %c
+}
+
+define <2 x double> @sqrt_v2f64(<2 x double> %a) {
+; CHECK-LABEL: sqrt_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fsqrt v0.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %c = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)
+ ret <2 x double> %c
+}
+
+define <3 x double> @sqrt_v3f64(<3 x double> %a) {
+; CHECK-SD-LABEL: sqrt_v3f64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: fsqrt v2.2d, v2.2d
+; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-SD-NEXT: fsqrt v0.2d, v0.2d
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqrt_v3f64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: fsqrt d2, d2
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: fsqrt v0.2d, v0.2d
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <3 x double> @llvm.sqrt.v3f64(<3 x double> %a)
+ ret <3 x double> %c
+}
+
+define <4 x double> @sqrt_v4f64(<4 x double> %a) {
+; CHECK-LABEL: sqrt_v4f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fsqrt v0.2d, v0.2d
+; CHECK-NEXT: fsqrt v1.2d, v1.2d
+; CHECK-NEXT: ret
+entry:
+ %c = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
+ ret <4 x double> %c
+}
+
+define <2 x float> @sqrt_v2f32(<2 x float> %a) {
+; CHECK-LABEL: sqrt_v2f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fsqrt v0.2s, v0.2s
+; CHECK-NEXT: ret
+entry:
+ %c = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %a)
+ ret <2 x float> %c
+}
+
+define <3 x float> @sqrt_v3f32(<3 x float> %a) {
+; CHECK-SD-LABEL: sqrt_v3f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fsqrt v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqrt_v3f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: mov s2, v0.s[2]
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
+; CHECK-GI-NEXT: fsqrt v0.4s, v0.4s
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: mov s2, v0.s[2]
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <3 x float> @llvm.sqrt.v3f32(<3 x float> %a)
+ ret <3 x float> %c
+}
+
+define <4 x float> @sqrt_v4f32(<4 x float> %a) {
+; CHECK-LABEL: sqrt_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fsqrt v0.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %c = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
+ ret <4 x float> %c
+}
+
+define <8 x float> @sqrt_v8f32(<8 x float> %a) {
+; CHECK-LABEL: sqrt_v8f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fsqrt v0.4s, v0.4s
+; CHECK-NEXT: fsqrt v1.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %c = call <8 x float> @llvm.sqrt.v8f32(<8 x float> %a)
+ ret <8 x float> %c
+}
+
+define <7 x half> @sqrt_v7f16(<7 x half> %a) {
+; CHECK-SD-NOFP16-LABEL: sqrt_v7f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h0
+; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[2]
+; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[3]
+; CHECK-SD-NOFP16-NEXT: mov h5, v0.h[4]
+; CHECK-SD-NOFP16-NEXT: mov h6, v0.h[5]
+; CHECK-SD-NOFP16-NEXT: mov h7, v0.h[6]
+; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]
+; CHECK-SD-NOFP16-NEXT: fcvt s1, h1
+; CHECK-SD-NOFP16-NEXT: fsqrt s2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h3
+; CHECK-SD-NOFP16-NEXT: fcvt s4, h4
+; CHECK-SD-NOFP16-NEXT: fcvt s5, h5
+; CHECK-SD-NOFP16-NEXT: fcvt s6, h6
+; CHECK-SD-NOFP16-NEXT: fcvt s7, h7
+; CHECK-SD-NOFP16-NEXT: fcvt s16, h0
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s2
+; CHECK-SD-NOFP16-NEXT: fsqrt s1, s1
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s1
+; CHECK-SD-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s3
+; CHECK-SD-NOFP16-NEXT: mov v0.h[2], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s4, s4
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s4
+; CHECK-SD-NOFP16-NEXT: mov v0.h[3], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s5, s5
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s5
+; CHECK-SD-NOFP16-NEXT: mov v0.h[4], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s6, s6
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s6
+; CHECK-SD-NOFP16-NEXT: mov v0.h[5], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s7, s7
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s7
+; CHECK-SD-NOFP16-NEXT: mov v0.h[6], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s2, s16
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s2
+; CHECK-SD-NOFP16-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: sqrt_v7f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fsqrt v0.8h, v0.8h
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: sqrt_v7f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov s2, v1.s[1]
+; CHECK-GI-NOFP16-NEXT: mov s3, v1.s[2]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[1], v2.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[2], v3.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[3], v0.s[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fsqrt v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: fsqrt v0.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: mov s2, v1.s[1]
+; CHECK-GI-NOFP16-NEXT: mov s3, v1.s[2]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[1], v2.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[2], v3.s[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.s[3], v0.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[1]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: sqrt_v7f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-FP16-NEXT: mov h6, v0.h[6]
+; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[3], v3.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[4], v4.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[5], v5.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[6], v6.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[7], v0.h[0]
+; CHECK-GI-FP16-NEXT: fsqrt v0.8h, v0.8h
+; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-FP16-NEXT: mov h6, v0.h[6]
+; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[3], v3.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[4], v4.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[5], v5.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[6], v6.h[0]
+; CHECK-GI-FP16-NEXT: mov v0.h[7], v0.h[0]
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call <7 x half> @llvm.sqrt.v7f16(<7 x half> %a)
+ ret <7 x half> %c
+}
+
+define <4 x half> @sqrt_v4f16(<4 x half> %a) {
+; CHECK-SD-NOFP16-LABEL: sqrt_v4f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h0
+; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[2]
+; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[3]
+; CHECK-SD-NOFP16-NEXT: fcvt s1, h1
+; CHECK-SD-NOFP16-NEXT: fsqrt s2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h3
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fsqrt s1, s1
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s1
+; CHECK-SD-NOFP16-NEXT: fsqrt s3, s3
+; CHECK-SD-NOFP16-NEXT: fsqrt s4, s0
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s2
+; CHECK-SD-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s3
+; CHECK-SD-NOFP16-NEXT: mov v0.h[2], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s4
+; CHECK-SD-NOFP16-NEXT: mov v0.h[3], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: sqrt_v4f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fsqrt v0.4h, v0.4h
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: sqrt_v4f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fsqrt v0.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: sqrt_v4f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: fsqrt v0.4h, v0.4h
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call <4 x half> @llvm.sqrt.v4f16(<4 x half> %a)
+ ret <4 x half> %c
+}
+
+define <8 x half> @sqrt_v8f16(<8 x half> %a) {
+; CHECK-SD-NOFP16-LABEL: sqrt_v8f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h0
+; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[2]
+; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[3]
+; CHECK-SD-NOFP16-NEXT: mov h5, v0.h[4]
+; CHECK-SD-NOFP16-NEXT: mov h6, v0.h[5]
+; CHECK-SD-NOFP16-NEXT: mov h7, v0.h[6]
+; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]
+; CHECK-SD-NOFP16-NEXT: fcvt s1, h1
+; CHECK-SD-NOFP16-NEXT: fsqrt s2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h3
+; CHECK-SD-NOFP16-NEXT: fcvt s4, h4
+; CHECK-SD-NOFP16-NEXT: fcvt s5, h5
+; CHECK-SD-NOFP16-NEXT: fcvt s6, h6
+; CHECK-SD-NOFP16-NEXT: fcvt s7, h7
+; CHECK-SD-NOFP16-NEXT: fcvt s16, h0
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s2
+; CHECK-SD-NOFP16-NEXT: fsqrt s1, s1
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s1
+; CHECK-SD-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s3
+; CHECK-SD-NOFP16-NEXT: mov v0.h[2], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s4, s4
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s4
+; CHECK-SD-NOFP16-NEXT: mov v0.h[3], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s5, s5
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s5
+; CHECK-SD-NOFP16-NEXT: mov v0.h[4], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s6, s6
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s6
+; CHECK-SD-NOFP16-NEXT: mov v0.h[5], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s7, s7
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s7
+; CHECK-SD-NOFP16-NEXT: mov v0.h[6], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s2, s16
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s2
+; CHECK-SD-NOFP16-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: sqrt_v8f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fsqrt v0.8h, v0.8h
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: sqrt_v8f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NOFP16-NEXT: fsqrt v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: fsqrt v2.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn2 v0.8h, v2.4s
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: sqrt_v8f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: fsqrt v0.8h, v0.8h
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)
+ ret <8 x half> %c
+}
+
+define <16 x half> @sqrt_v16f16(<16 x half> %a) {
+; CHECK-SD-NOFP16-LABEL: sqrt_v16f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h0
+; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[2]
+; CHECK-SD-NOFP16-NEXT: mov h5, v0.h[3]
+; CHECK-SD-NOFP16-NEXT: mov h6, v0.h[4]
+; CHECK-SD-NOFP16-NEXT: mov h7, v0.h[5]
+; CHECK-SD-NOFP16-NEXT: mov h16, v0.h[6]
+; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h2
+; CHECK-SD-NOFP16-NEXT: fsqrt s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt s4, h4
+; CHECK-SD-NOFP16-NEXT: fcvt s5, h5
+; CHECK-SD-NOFP16-NEXT: fcvt s6, h6
+; CHECK-SD-NOFP16-NEXT: fcvt s7, h7
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fcvt s16, h16
+; CHECK-SD-NOFP16-NEXT: fsqrt s17, s0
+; CHECK-SD-NOFP16-NEXT: mov h0, v1.h[1]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fsqrt s18, s0
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h1
+; CHECK-SD-NOFP16-NEXT: fcvt h18, s18
+; CHECK-SD-NOFP16-NEXT: fsqrt s19, s0
+; CHECK-SD-NOFP16-NEXT: mov h0, v1.h[2]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fsqrt s20, s0
+; CHECK-SD-NOFP16-NEXT: mov h0, v1.h[3]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fsqrt s21, s0
+; CHECK-SD-NOFP16-NEXT: mov h0, v1.h[4]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fsqrt s2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s2
+; CHECK-SD-NOFP16-NEXT: fsqrt s4, s4
+; CHECK-SD-NOFP16-NEXT: fsqrt s22, s0
+; CHECK-SD-NOFP16-NEXT: mov h0, v1.h[5]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fsqrt s5, s5
+; CHECK-SD-NOFP16-NEXT: fsqrt s6, s6
+; CHECK-SD-NOFP16-NEXT: fsqrt s23, s0
+; CHECK-SD-NOFP16-NEXT: mov h0, v1.h[6]
+; CHECK-SD-NOFP16-NEXT: mov h1, v1.h[7]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fsqrt s7, s7
+; CHECK-SD-NOFP16-NEXT: fsqrt s16, s16
+; CHECK-SD-NOFP16-NEXT: fsqrt s24, s0
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s3
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h1
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s19
+; CHECK-SD-NOFP16-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s4
+; CHECK-SD-NOFP16-NEXT: mov v1.h[1], v18.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s20
+; CHECK-SD-NOFP16-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s5
+; CHECK-SD-NOFP16-NEXT: mov v1.h[2], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s21
+; CHECK-SD-NOFP16-NEXT: mov v0.h[3], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s6
+; CHECK-SD-NOFP16-NEXT: mov v1.h[3], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s22
+; CHECK-SD-NOFP16-NEXT: mov v0.h[4], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s7
+; CHECK-SD-NOFP16-NEXT: mov v1.h[4], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s23
+; CHECK-SD-NOFP16-NEXT: mov v0.h[5], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s16
+; CHECK-SD-NOFP16-NEXT: mov v1.h[5], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s24
+; CHECK-SD-NOFP16-NEXT: mov v0.h[6], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s17
+; CHECK-SD-NOFP16-NEXT: mov v1.h[6], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: mov v0.h[7], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fsqrt s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt h3, s3
+; CHECK-SD-NOFP16-NEXT: mov v1.h[7], v3.h[0]
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: sqrt_v16f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fsqrt v0.8h, v0.8h
+; CHECK-SD-FP16-NEXT: fsqrt v1.8h, v1.8h
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: sqrt_v16f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NOFP16-NEXT: fsqrt v3.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: fsqrt v2.4s, v2.4s
+; CHECK-GI-NOFP16-NEXT: fsqrt v4.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v1.8h
+; CHECK-GI-NOFP16-NEXT: fsqrt v5.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v4.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn2 v0.8h, v3.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn2 v1.8h, v5.4s
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: sqrt_v16f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: fsqrt v0.8h, v0.8h
+; CHECK-GI-FP16-NEXT: fsqrt v1.8h, v1.8h
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call <16 x half> @llvm.sqrt.v16f16(<16 x half> %a)
+ ret <16 x half> %c
+}
+
+declare <16 x half> @llvm.sqrt.v16f16(<16 x half>)
+declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)
+declare <2 x float> @llvm.sqrt.v2f32(<2 x float>)
+declare <3 x double> @llvm.sqrt.v3f64(<3 x double>)
+declare <3 x float> @llvm.sqrt.v3f32(<3 x float>)
+declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)
+declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
+declare <4 x half> @llvm.sqrt.v4f16(<4 x half>)
+declare <7 x half> @llvm.sqrt.v7f16(<7 x half>)
+declare <8 x float> @llvm.sqrt.v8f32(<8 x float>)
+declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)
+declare double @llvm.sqrt.f64(double)
+declare float @llvm.sqrt.f32(float)
+declare half @llvm.sqrt.f16(half)
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