[PATCH] D155484: [AArch64] Global Isel Funnel Shift Lowering

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:1036-1038
+  // Deal with this case in the optimizer (Combine.td)
+  if (Amount == 0)
+    return false;
----------------
This looks like it is already checked above


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:1044-1046
+      VRegAndVal->Value.ult(BitWidth)) {
+    return true;
+  }
----------------
This can drop the { } brackets from single statement if blocks.


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:1048-1049
+
+  // Modulo the shift amount by the bit width
+  // Amount = Amount.urem(BitWidth);
+
----------------
This can be removed too now.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155484/new/

https://reviews.llvm.org/D155484