[PATCH] D157624: [AMDGPU] Treat KIMM32 and KIMM16 operand types as noninlinable

[Mirko Brkusanin via Phabricator via llvm-commits]

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While they are 32bit literals they are already included in encoding of the
instructions that use them and do not increase the size of the instruction from
their base size.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157624

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/code-size-estimate.ll


Index: llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
+++ llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
@@ -149,6 +149,7 @@
 
 ; GFX9: codeLenInByte = 24
 ; GFX10: codeLenInByte = 20
+; GFX11: codeLenInByte = 20
 
 define float @v_mul_f32_vop2_frame_index(float %x) {
 ; GFX9-LABEL: v_mul_f32_vop2_frame_index:
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3906,6 +3906,7 @@
   }
   case AMDGPU::OPERAND_KIMM32:
   case AMDGPU::OPERAND_KIMM16:
+    return false;
   case AMDGPU::OPERAND_INPUT_MODS:
   case MCOI::OPERAND_IMMEDIATE:
     // Always embedded in the instruction for free.
@@ -7818,7 +7819,9 @@
     for (int I = 0, E = MI.getNumExplicitOperands(); I != E; ++I) {
       const MachineOperand &Op = MI.getOperand(I);
       const MCOperandInfo &OpInfo = Desc.operands()[I];
-      if (!Op.isReg() && !isInlineConstant(Op, OpInfo)) {
+      if (!Op.isReg() && !isInlineConstant(Op, OpInfo) &&
+          OpInfo.OperandType != AMDGPU::OPERAND_KIMM16 &&
+          OpInfo.OperandType != AMDGPU::OPERAND_KIMM32) {
         HasLiteral = true;
         break;
       }


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