[PATCH] D157614: [RISCV] Lower reverse shuffles of fixed i1 vectors to vbrev.v

[Luke Lau via Phabricator via llvm-commits]

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If we can fit an entire vector of i1 into a single element, e.g. v32i1 ->
v1i32, then we can reverse it via vbrev.v.
We need to handle the case where the vector doesn't exactly fit into the larger
element type, e.g. v4i1 -> v1i8. In this case we shift up the reversed bits
afterwards.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157614

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll

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