[PATCH] D156685: [RISCV] Match ext + ext + srem + trunc to vrem.vv

[Vettel via Phabricator via llvm-commits]

LWenH updated this revision to Diff 548933.
LWenH retitled this revision from "[RISCV]  Match  ext_vl + ext_vl + srem + trunc_vl to vrem.vv" to "[RISCV]  Match  ext + ext + srem + trunc to vrem.vv".
LWenH edited the summary of this revision.
LWenH added a comment.

Address @craig.topper and @Jim 's comments. Update and add  precommit test for this patch.

Actually, such signed operation can't be removed before the instruction phase. Such a signed extension and trunc operation in LLVM System is to prevent Undefined Behavior. Taking an example, -128 % -1 will lead to the Undefined Behaviour(overflowed) under the i8 type in LLVM IR, but this won't happen for i32. So LLVM first extend this to i32 to prevent UB for operation like -128 % -1, and such pattern for unsign actually can be able to removed during the instcombine pass, because the zext + urem + trunc won't lead to the overflowed in LLVM. For RVV, such overflow operation has been defined in the spec and have the determined output. For example, base on the spec, for the i8 type, -128 % -1 actually have 0 as the output result. So, I'm thinking for the rvv backend, we can remove such pattern to shrink the codesize.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156685/new/

https://reviews.llvm.org/D156685

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

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