[PATCH] D157592: Add Precommit test for D156685

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LWenH created this revision.
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Add baseline test for D156685 <https://reviews.llvm.org/D156685>.

In LLVM, such signed 8 bits reaminder operation will first signed extened the operands to 32 bits, then then narrow the operand to a smaller number of bits such as 16 bits in the CorrelatedValuePropagation Pass to optimize the final data storage size.  Such a signed extension operation in LLVM System is to prevent Undefined Behavior.  Taking an example, -128 % -1 will lead to the Undefined Behaviour under the i8 type in LLVM IR, but this won't happen for i32, so such pattern cannot be eliminated in the platform-independent InstCombine Pass. The LLVM IR of these sext/trunc operations will be translated one by one during the RVV backend code generation process, and redundant vsetvli instructions will be inserted.

In fact, according to the RVV instruction manual, the vrem.vv instruction has already specified the final output value of this type of overflow operation. For example, the overflow operation of -128 % -1 will get 0 according to the RISC-V spec, so through this patch , I think we can optimize these redundant rvv code through the SDNode pattern match at the instruction selection phase.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157592

Files:
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

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