[PATCH] D156615: [AArch64][GISel] Add handling for G_VECREDUCE_FMAXIMUM and G_VECREDUCE_FMINIMUM

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 548928.
dmgreen added a comment.

Rebase and add a couple of extra legalization tests.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156615/new/

https://reviews.llvm.org/D156615

Files:
  llvm/docs/GlobalISel/GenericOpcode.rst
  llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
  llvm/include/llvm/CodeGen/GlobalISel/Utils.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/GenericOpcodes.td
  llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fminmax.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
  llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
  llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll

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