[llvm] 7e39e2e - [DirectX,SPIRV] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2023-08-09T15:24:58-07:00
New Revision: 7e39e2e5190cde3091e774224304b90177e4eb3d

URL: https://github.com/llvm/llvm-project/commit/7e39e2e5190cde3091e774224304b90177e4eb3d
DIFF: https://github.com/llvm/llvm-project/commit/7e39e2e5190cde3091e774224304b90177e4eb3d.diff

LOG: [DirectX,SPIRV] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC

Added: 
    

Modified: 
    llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp
    llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp b/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp
index cb6d4c5cd0a3ba..77007d853d95d9 100644
--- a/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp
+++ b/llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp
@@ -64,7 +64,7 @@ class DXILMCCodeEmitter : public MCCodeEmitter {
 public:
   DXILMCCodeEmitter() {}
 
-  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
+  void encodeInstruction(const MCInst &Inst, SmallVectorImpl<char> &CB,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override {}
 };

diff  --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index 5555adc1901014..60b68dea934adc 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -43,7 +43,7 @@ class SPIRVMCCodeEmitter : public MCCodeEmitter {
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 
-  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
+  void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
 };
@@ -74,12 +74,14 @@ static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
   return false;
 }
 
-static void emitOperand(const MCOperand &Op, EndianWriter &OSE) {
+static void emitOperand(const MCOperand &Op, SmallVectorImpl<char> &CB) {
   if (Op.isReg()) {
     // Emit the id index starting at 1 (0 is an invalid index).
-    OSE.write<uint32_t>(Register::virtReg2Index(Op.getReg()) + 1);
+    support::endian::write<uint32_t>(
+        CB, Register::virtReg2Index(Op.getReg()) + 1, support::little);
   } else if (Op.isImm()) {
-    OSE.write<uint32_t>(Op.getImm());
+    support::endian::write(CB, static_cast<uint32_t>(Op.getImm()),
+                           support::little);
   } else {
     llvm_unreachable("Unexpected operand type in VReg");
   }
@@ -87,36 +89,37 @@ static void emitOperand(const MCOperand &Op, EndianWriter &OSE) {
 
 // Emit the type in operand 1 before the ID in operand 0 it defines, and all
 // remaining operands in the order they come naturally.
-static void emitTypedInstrOperands(const MCInst &MI, EndianWriter &OSE) {
+static void emitTypedInstrOperands(const MCInst &MI,
+                                   SmallVectorImpl<char> &CB) {
   unsigned NumOps = MI.getNumOperands();
-  emitOperand(MI.getOperand(1), OSE);
-  emitOperand(MI.getOperand(0), OSE);
+  emitOperand(MI.getOperand(1), CB);
+  emitOperand(MI.getOperand(0), CB);
   for (unsigned i = 2; i < NumOps; ++i)
-    emitOperand(MI.getOperand(i), OSE);
+    emitOperand(MI.getOperand(i), CB);
 }
 
 // Emit operands in the order they come naturally.
-static void emitUntypedInstrOperands(const MCInst &MI, EndianWriter &OSE) {
+static void emitUntypedInstrOperands(const MCInst &MI,
+                                     SmallVectorImpl<char> &CB) {
   for (const auto &Op : MI)
-    emitOperand(Op, OSE);
+    emitOperand(Op, CB);
 }
 
-void SPIRVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
+void SPIRVMCCodeEmitter::encodeInstruction(const MCInst &MI,
+                                           SmallVectorImpl<char> &CB,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
-  EndianWriter OSE(OS, support::little);
-
   // Encode the first 32 SPIR-V bytes with the number of args and the opcode.
   const uint64_t OpCode = getBinaryCodeForInstr(MI, Fixups, STI);
   const uint32_t NumWords = MI.getNumOperands() + 1;
   const uint32_t FirstWord = (NumWords << 16) | OpCode;
-  OSE.write<uint32_t>(FirstWord);
+  support::endian::write(CB, FirstWord, support::little);
 
   // Emit the instruction arguments (emitting the output type first if present).
   if (hasType(MI, MCII))
-    emitTypedInstrOperands(MI, OSE);
+    emitTypedInstrOperands(MI, CB);
   else
-    emitUntypedInstrOperands(MI, OSE);
+    emitUntypedInstrOperands(MI, CB);
 }
 
 #include "SPIRVGenMCCodeEmitter.inc"