[PATCH] D157549: [LV] Add debug output to print interleaved groups

[Anna Thomas via Phabricator via llvm-commits]

anna created this revision.
anna added reviewers: Ayal, fhahn.
Herald added subscribers: artagnon, StephenFan, hiraditya.
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Herald added a project: LLVM.

Add interleaved groups available after interleave analysis is done.
See updated tests.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157549

Files:
  llvm/include/llvm/Analysis/VectorUtils.h
  llvm/lib/Analysis/VectorUtils.cpp
  llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-use-after-free.ll
  llvm/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll


Index: llvm/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll
+++ llvm/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll
@@ -1,4 +1,4 @@
-; RUN: opt -passes=loop-vectorize -mcpu=corei7-avx -debug -S < %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -mcpu=corei7-avx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
 ; REQUIRES: asserts
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
Index: llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-use-after-free.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-use-after-free.ll
+++ llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-use-after-free.ll
@@ -1,6 +1,6 @@
 ; REQUIRES: asserts
 ; RUN: opt -passes=loop-vectorize -debug-only=loop-accesses -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s -check-prefix=LOOP-ACCESS
-; RUN: opt -passes=loop-vectorize -debug-only=vectorutils -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -debug-only=vectorutils -debug-only=vectorutils-verbose -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-redhat-linux-gnu"
 
@@ -42,7 +42,11 @@
 ; CHECK:     into the interleave group with  store ptr null, ptr %getelementptr13
 ; CHECK: LV: Invalidated store group due to dependence between   store ptr %load7, ptr %getelementptr, align 8 and   store ptr null, ptr %getelementptr13, align 8
 ; CHECK-NOT: LV: Invalidated store group due to dependence between
-
+; CHECK: Interleaved Groups
+; CHECK: Group with members: 
+; CHECK:   %load7 = load ptr, ptr %phi6, align 8
+; CHECK: Group with members: 
+; CHECK:   %load12 = load ptr, ptr %phi6, align 8
 ; Note: The (only) invalidated store group is the one containing A (store ptr %load7, ptr %getelementptr, align 8) which is:
 ; Group with instructions:  
 ;   store ptr null, ptr %phi5, align 8
Index: llvm/lib/Analysis/VectorUtils.cpp
===================================================================
--- llvm/lib/Analysis/VectorUtils.cpp
+++ llvm/lib/Analysis/VectorUtils.cpp
@@ -28,6 +28,8 @@
 
 #define DEBUG_TYPE "vectorutils"
 
+const char VerboseDebug[] = DEBUG_TYPE "-verbose";
+
 using namespace llvm;
 using namespace llvm::PatternMatch;
 
@@ -1410,6 +1412,16 @@
         break;
       }
   }
+  // Print out all load and store groups
+  DEBUG_WITH_TYPE(VerboseDebug, {
+      dbgs() << "Interleaved Groups\n";
+  for (InterleaveGroup<Instruction> *IG : getInterleaveGroups()) {
+    dbgs() << "Group with members: "<< "\n";
+    for (auto *I : IG->getMembers()) {
+      dbgs() << *I << "\n";
+    }    
+  }
+  });
 }
 
 void InterleavedAccessInfo::invalidateGroupsRequiringScalarEpilogue() {
Index: llvm/include/llvm/Analysis/VectorUtils.h
===================================================================
--- llvm/include/llvm/Analysis/VectorUtils.h
+++ llvm/include/llvm/Analysis/VectorUtils.h
@@ -651,6 +651,12 @@
   uint32_t getFactor() const { return Factor; }
   Align getAlign() const { return Alignment; }
   uint32_t getNumMembers() const { return Members.size(); }
+  SmallVector<InstTy *> getMembers() const {
+    SmallVector<InstTy *> Mems;
+    for (auto &It : Members)
+      Mems.push_back(It.second);
+    return Mems;
+  }
 
   /// Try to insert a new member \p Instr with index \p Index and
   /// alignment \p NewAlign. The index is related to the leader and it could be


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