[llvm] 84e89c9 - [ARM] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2023-08-09T09:25:43-07:00
New Revision: 84e89c9e0640de4cb946d126723d2038b74e2ea0

URL: https://github.com/llvm/llvm-project/commit/84e89c9e0640de4cb946d126723d2038b74e2ea0
DIFF: https://github.com/llvm/llvm-project/commit/84e89c9e0640de4cb946d126723d2038b74e2ea0.diff

LOG: [ARM] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC

Added: 
    

Modified: 
    llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index dae323ec24fb13..a35196c199a506 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -29,6 +29,7 @@
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
+#include "llvm/Support/EndianStream.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
@@ -436,19 +437,7 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
 
-  void EmitByte(unsigned char C, raw_ostream &OS) const {
-    OS << (char)C;
-  }
-
-  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
-    // Output the constant in little endian byte order.
-    for (unsigned i = 0; i != Size; ++i) {
-      unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
-      EmitByte((Val >> Shift) & 0xff, OS);
-    }
-  }
-
-  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
+  void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
 
@@ -1894,10 +1883,10 @@ getShiftRight64Imm(const MCInst &MI, unsigned Op,
   return 64 - MI.getOperand(Op).getImm();
 }
 
-void ARMMCCodeEmitter::
-encodeInstruction(const MCInst &MI, raw_ostream &OS,
-                  SmallVectorImpl<MCFixup> &Fixups,
-                  const MCSubtargetInfo &STI) const {
+void ARMMCCodeEmitter::encodeInstruction(const MCInst &MI,
+                                         SmallVectorImpl<char> &CB,
+                                         SmallVectorImpl<MCFixup> &Fixups,
+                                         const MCSubtargetInfo &STI) const {
   // Pseudo instructions don't get encoded.
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   uint64_t TSFlags = Desc.TSFlags;
@@ -1910,14 +1899,18 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
   else
     llvm_unreachable("Unexpected instruction size!");
 
+  auto Endian = IsLittleEndian ? support::little : support::big;
   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
-  // Thumb 32-bit wide instructions need to emit the high order halfword
-  // first.
-  if (isThumb(STI) && Size == 4) {
-    EmitConstant(Binary >> 16, 2, OS);
-    EmitConstant(Binary & 0xffff, 2, OS);
-  } else
-    EmitConstant(Binary, Size, OS);
+  if (Size == 2) {
+    support::endian::write<uint16_t>(CB, Binary, Endian);
+  } else if (isThumb(STI)) {
+    // Thumb 32-bit wide instructions need to emit the high order halfword
+    // first.
+    support::endian::write<uint16_t>(CB, Binary >> 16, Endian);
+    support::endian::write<uint16_t>(CB, Binary & 0xffff, Endian);
+  } else {
+    support::endian::write<uint32_t>(CB, Binary, Endian);
+  }
   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
 }