[llvm] 2bb7272 - [AArch64] Regenerate s/urem-seteq-* tests. NFC

David Green via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 8 13:34:39 PDT 2023


Author: David Green
Date: 2023-08-08T21:34:34+01:00
New Revision: 2bb727297d9afb432455160f57e7e14a4a36db70

URL: https://github.com/llvm/llvm-project/commit/2bb727297d9afb432455160f57e7e14a4a36db70
DIFF: https://github.com/llvm/llvm-project/commit/2bb727297d9afb432455160f57e7e14a4a36db70.diff

LOG: [AArch64] Regenerate s/urem-seteq-* tests. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
    llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
    llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
    llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
    llvm/test/CodeGen/AArch64/srem-seteq.ll
    llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
    llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
    llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
    llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
    llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
    llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
    llvm/test/CodeGen/AArch64/urem-seteq.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
index 9803e9487b9678..b607af42339f63 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
@@ -4,12 +4,12 @@
 define i1 @test_srem_odd(i29 %X) nounwind {
 ; CHECK-LABEL: test_srem_odd:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #33099
-; CHECK-NEXT:    mov w9, #24493
+; CHECK-NEXT:    mov w8, #33099 // =0x814b
+; CHECK-NEXT:    mov w9, #24493 // =0x5fad
 ; CHECK-NEXT:    movk w8, #8026, lsl #16
 ; CHECK-NEXT:    movk w9, #41, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #48987
+; CHECK-NEXT:    mov w9, #48987 // =0xbf5b
 ; CHECK-NEXT:    movk w9, #82, lsl #16
 ; CHECK-NEXT:    and w8, w8, #0x1fffffff
 ; CHECK-NEXT:    cmp w8, w9
@@ -24,7 +24,7 @@ define i1 @test_srem_even(i4 %X) nounwind {
 ; CHECK-LABEL: test_srem_even:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sbfx w9, w0, #0, #4
-; CHECK-NEXT:    mov w8, #6
+; CHECK-NEXT:    mov w8, #6 // =0x6
 ; CHECK-NEXT:    add w9, w9, w9, lsl #1
 ; CHECK-NEXT:    ubfx w10, w9, #7, #1
 ; CHECK-NEXT:    add w9, w10, w9, lsr #4
@@ -57,10 +57,10 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
 define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
 ; CHECK-LABEL: test_srem_vec:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #7282
+; CHECK-NEXT:    mov x8, #7282 // =0x1c72
 ; CHECK-NEXT:    sbfx x9, x0, #0, #33
 ; CHECK-NEXT:    movk x8, #29127, lsl #16
-; CHECK-NEXT:    mov x11, #7281
+; CHECK-NEXT:    mov x11, #7281 // =0x1c71
 ; CHECK-NEXT:    movk x8, #50972, lsl #32
 ; CHECK-NEXT:    movk x11, #29127, lsl #16
 ; CHECK-NEXT:    movk x8, #7281, lsl #48
@@ -83,7 +83,7 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
 ; CHECK-NEXT:    add x11, x11, x11, lsl #3
 ; CHECK-NEXT:    fmov d0, x9
 ; CHECK-NEXT:    add x10, x10, x11
-; CHECK-NEXT:    mov x9, #8589934591
+; CHECK-NEXT:    mov x9, #8589934591 // =0x1ffffffff
 ; CHECK-NEXT:    adrp x11, .LCPI3_0
 ; CHECK-NEXT:    adrp x12, .LCPI3_1
 ; CHECK-NEXT:    mov v0.d[1], x8

diff  --git a/llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll b/llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
index a1283de01bdcf1..8a41482b016529 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
@@ -4,12 +4,12 @@
 define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
 ; CHECK-LABEL: test_minsize:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5
-; CHECK-NEXT:    mov w9, #42
+; CHECK-NEXT:    mov w8, #5 // =0x5
+; CHECK-NEXT:    mov w9, #42 // =0x2a
 ; CHECK-NEXT:    sdiv w8, w0, w8
 ; CHECK-NEXT:    add w8, w8, w8, lsl #2
 ; CHECK-NEXT:    cmp w0, w8
-; CHECK-NEXT:    mov w8, #-10
+; CHECK-NEXT:    mov w8, #-10 // =0xfffffff6
 ; CHECK-NEXT:    csel w0, w9, w8, eq
 ; CHECK-NEXT:    ret
   %rem = srem i32 %X, 5
@@ -21,15 +21,15 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
 define i32 @test_optsize(i32 %X) optsize nounwind readnone {
 ; CHECK-LABEL: test_optsize:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #39321
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #39321 // =0x9999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #6553, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #858993459
+; CHECK-NEXT:    mov w9, #858993459 // =0x33333333
 ; CHECK-NEXT:    cmp w8, w9
-; CHECK-NEXT:    mov w8, #-10
-; CHECK-NEXT:    mov w9, #42
+; CHECK-NEXT:    mov w8, #-10 // =0xfffffff6
+; CHECK-NEXT:    mov w9, #42 // =0x2a
 ; CHECK-NEXT:    csel w0, w9, w8, lo
 ; CHECK-NEXT:    ret
   %rem = srem i32 %X, 5

diff  --git a/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
index bd6145d1bca66d..e75d220ed21459 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
@@ -35,8 +35,8 @@ define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_allones_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #39321
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #39321 // =0x9999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #6553, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -56,8 +56,8 @@ define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_allones_ne:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #39321
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #39321 // =0x9999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #6553, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -79,8 +79,8 @@ define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_even_allones_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28087
-; CHECK-NEXT:    mov w9, #9362
+; CHECK-NEXT:    mov w8, #28087 // =0x6db7
+; CHECK-NEXT:    mov w9, #9362 // =0x2492
 ; CHECK-NEXT:    movk w8, #46811, lsl #16
 ; CHECK-NEXT:    movk w9, #4681, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #1
@@ -103,8 +103,8 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_even_allones_ne:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28087
-; CHECK-NEXT:    mov w9, #9362
+; CHECK-NEXT:    mov w8, #28087 // =0x6db7
+; CHECK-NEXT:    mov w9, #9362 // =0x2492
 ; CHECK-NEXT:    movk w8, #46811, lsl #16
 ; CHECK-NEXT:    movk w9, #4681, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #1
@@ -271,8 +271,8 @@ define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #39321
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #39321 // =0x9999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #6553, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -294,8 +294,8 @@ define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_even_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28087
-; CHECK-NEXT:    mov w9, #9362
+; CHECK-NEXT:    mov w8, #28087 // =0x6db7
+; CHECK-NEXT:    mov w9, #9362 // =0x2492
 ; CHECK-NEXT:    movk w8, #46811, lsl #16
 ; CHECK-NEXT:    movk w9, #4681, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #1
@@ -525,8 +525,8 @@ define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
 define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_allones_and_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #39321
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #39321 // =0x9999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #6553, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -548,8 +548,8 @@ define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_even_allones_and_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28087
-; CHECK-NEXT:    mov w9, #9362
+; CHECK-NEXT:    mov w8, #28087 // =0x6db7
+; CHECK-NEXT:    mov w9, #9362 // =0x2492
 ; CHECK-NEXT:    movk w8, #46811, lsl #16
 ; CHECK-NEXT:    movk w9, #4681, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #1

diff  --git a/llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll b/llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
index c6f7377794413e..ce71f09062cd3f 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
@@ -5,13 +5,13 @@
 define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_25:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
-; CHECK-NEXT:    mov w9, #47185
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
+; CHECK-NEXT:    mov w9, #47185 // =0xb851
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movk w9, #1310, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    dup v2.4s, w9
-; CHECK-NEXT:    mov w8, #28834
+; CHECK-NEXT:    mov w8, #28834 // =0x70a2
 ; CHECK-NEXT:    movk w8, #2621, lsl #16
 ; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    movi v1.4s, #1
@@ -29,14 +29,14 @@ define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_even_100:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
-; CHECK-NEXT:    mov w9, #47184
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
+; CHECK-NEXT:    mov w9, #47184 // =0xb850
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movk w9, #1310, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #1
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    dup v2.4s, w9
-; CHECK-NEXT:    mov w8, #23592
+; CHECK-NEXT:    mov w8, #23592 // =0x5c28
 ; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    movk w8, #655, lsl #16
 ; CHECK-NEXT:    shl v0.4s, v2.4s, #30
@@ -58,13 +58,13 @@ define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_neg25:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
-; CHECK-NEXT:    mov w9, #47185
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
+; CHECK-NEXT:    mov w9, #47185 // =0xb851
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movk w9, #1310, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    dup v2.4s, w9
-; CHECK-NEXT:    mov w8, #28834
+; CHECK-NEXT:    mov w8, #28834 // =0x70a2
 ; CHECK-NEXT:    movk w8, #2621, lsl #16
 ; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    movi v1.4s, #1
@@ -82,14 +82,14 @@ define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_even_neg100:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
-; CHECK-NEXT:    mov w9, #47184
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
+; CHECK-NEXT:    mov w9, #47184 // =0xb850
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movk w9, #1310, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #1
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    dup v2.4s, w9
-; CHECK-NEXT:    mov w8, #23592
+; CHECK-NEXT:    mov w8, #23592 // =0x5c28
 ; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    movk w8, #655, lsl #16
 ; CHECK-NEXT:    shl v0.4s, v2.4s, #30
@@ -112,7 +112,7 @@ define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_undef1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #34079
+; CHECK-NEXT:    mov w8, #34079 // =0x851f
 ; CHECK-NEXT:    movk w8, #20971, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #25
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -135,7 +135,7 @@ define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
 define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_srem_even_undef1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #34079
+; CHECK-NEXT:    mov w8, #34079 // =0x851f
 ; CHECK-NEXT:    movk w8, #20971, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #100
 ; CHECK-NEXT:    dup v1.4s, w8

diff  --git a/llvm/test/CodeGen/AArch64/srem-seteq.ll b/llvm/test/CodeGen/AArch64/srem-seteq.ll
index 4bb29d344282f2..4b8cbc46a6102e 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq.ll
@@ -8,12 +8,12 @@
 define i32 @test_srem_odd(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_odd:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #39321
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #39321 // =0x9999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #6553, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #858993459
+; CHECK-NEXT:    mov w9, #858993459 // =0x33333333
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    cset w0, lo
 ; CHECK-NEXT:    ret
@@ -26,12 +26,12 @@ define i32 @test_srem_odd(i32 %X) nounwind {
 define i32 @test_srem_odd_25(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_25:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
-; CHECK-NEXT:    mov w9, #47185
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
+; CHECK-NEXT:    mov w9, #47185 // =0xb851
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movk w9, #1310, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #28835
+; CHECK-NEXT:    mov w9, #28835 // =0x70a3
 ; CHECK-NEXT:    movk w9, #2621, lsl #16
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    cset w0, lo
@@ -46,8 +46,8 @@ define i32 @test_srem_odd_25(i32 %X) nounwind {
 define i32 @test_srem_odd_bit30(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_bit30:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
-; CHECK-NEXT:    mov w9, #1
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
+; CHECK-NEXT:    mov w9, #1 // =0x1
 ; CHECK-NEXT:    movk w8, #27306, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
 ; CHECK-NEXT:    cmp w8, #3
@@ -63,8 +63,8 @@ define i32 @test_srem_odd_bit30(i32 %X) nounwind {
 define i32 @test_srem_odd_bit31(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_bit31:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #21845
-; CHECK-NEXT:    mov w9, #1
+; CHECK-NEXT:    mov w8, #21845 // =0x5555
+; CHECK-NEXT:    mov w9, #1 // =0x1
 ; CHECK-NEXT:    movk w8, #54613, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
 ; CHECK-NEXT:    cmp w8, #3
@@ -83,8 +83,8 @@ define i32 @test_srem_odd_bit31(i32 %X) nounwind {
 define i16 @test_srem_even(i16 %X) nounwind {
 ; CHECK-LABEL: test_srem_even:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28087
-; CHECK-NEXT:    mov w9, #4680
+; CHECK-NEXT:    mov w8, #28087 // =0x6db7
+; CHECK-NEXT:    mov w9, #4680 // =0x1248
 ; CHECK-NEXT:    madd w8, w0, w8, w9
 ; CHECK-NEXT:    lsl w10, w8, #15
 ; CHECK-NEXT:    bfxil w10, w8, #1, #15
@@ -100,12 +100,12 @@ define i16 @test_srem_even(i16 %X) nounwind {
 define i32 @test_srem_even_100(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_even_100:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
-; CHECK-NEXT:    mov w9, #47184
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
+; CHECK-NEXT:    mov w9, #47184 // =0xb850
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movk w9, #1310, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #23593
+; CHECK-NEXT:    mov w9, #23593 // =0x5c29
 ; CHECK-NEXT:    movk w9, #655, lsl #16
 ; CHECK-NEXT:    ror w8, w8, #2
 ; CHECK-NEXT:    cmp w8, w9
@@ -121,8 +121,8 @@ define i32 @test_srem_even_100(i32 %X) nounwind {
 define i32 @test_srem_even_bit30(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_even_bit30:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #20165
-; CHECK-NEXT:    mov w9, #8
+; CHECK-NEXT:    mov w8, #20165 // =0x4ec5
+; CHECK-NEXT:    mov w9, #8 // =0x8
 ; CHECK-NEXT:    movk w8, #64748, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
 ; CHECK-NEXT:    ror w8, w8, #3
@@ -139,8 +139,8 @@ define i32 @test_srem_even_bit30(i32 %X) nounwind {
 define i32 @test_srem_even_bit31(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_even_bit31:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1285
-; CHECK-NEXT:    mov w9, #2
+; CHECK-NEXT:    mov w8, #1285 // =0x505
+; CHECK-NEXT:    mov w9, #2 // =0x2
 ; CHECK-NEXT:    movk w8, #50437, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
 ; CHECK-NEXT:    ror w8, w8, #1
@@ -161,12 +161,12 @@ define i32 @test_srem_even_bit31(i32 %X) nounwind {
 define i32 @test_srem_odd_setne(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_odd_setne:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #39321
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #39321 // =0x9999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #6553, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #13106
+; CHECK-NEXT:    mov w9, #13106 // =0x3332
 ; CHECK-NEXT:    movk w9, #13107, lsl #16
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    cset w0, hi
@@ -181,12 +181,12 @@ define i32 @test_srem_odd_setne(i32 %X) nounwind {
 define i32 @test_srem_negative_odd(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_negative_odd:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #39321
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #39321 // =0x9999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #6553, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #13106
+; CHECK-NEXT:    mov w9, #13106 // =0x3332
 ; CHECK-NEXT:    movk w9, #13107, lsl #16
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    cset w0, hi
@@ -199,8 +199,8 @@ define i32 @test_srem_negative_odd(i32 %X) nounwind {
 define i32 @test_srem_negative_even(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_negative_even:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28087
-; CHECK-NEXT:    mov w9, #9362
+; CHECK-NEXT:    mov w8, #28087 // =0x6db7
+; CHECK-NEXT:    mov w9, #9362 // =0x2492
 ; CHECK-NEXT:    movk w8, #46811, lsl #16
 ; CHECK-NEXT:    movk w9, #4681, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
@@ -222,7 +222,7 @@ define i32 @test_srem_negative_even(i32 %X) nounwind {
 define i32 @test_srem_one(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #1
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
   %srem = srem i32 %X, 1
   %cmp = icmp eq i32 %srem, 0
@@ -268,7 +268,7 @@ define i32 @test_srem_int_min(i32 %X) nounwind {
 define i32 @test_srem_allones(i32 %X) nounwind {
 ; CHECK-LABEL: test_srem_allones:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #1
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
   %srem = srem i32 %X, 4294967295
   %cmp = icmp eq i32 %srem, 0

diff  --git a/llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll b/llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
index b3be59dd7b0820..eb2e61d1c25a39 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
@@ -4,8 +4,8 @@
 define i1 @t32_3_1(i32 %X) nounwind {
 ; CHECK-LABEL: t32_3_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
-; CHECK-NEXT:    mov w9, #1431655765
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
+; CHECK-NEXT:    mov w9, #1431655765 // =0x55555555
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
 ; CHECK-NEXT:    cmp w8, w9
@@ -19,11 +19,11 @@ define i1 @t32_3_1(i32 %X) nounwind {
 define i1 @t32_3_2(i32 %X) nounwind {
 ; CHECK-LABEL: t32_3_2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
-; CHECK-NEXT:    mov w9, #-1431655766
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
+; CHECK-NEXT:    mov w9, #-1431655766 // =0xaaaaaaaa
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #1431655765
+; CHECK-NEXT:    mov w9, #1431655765 // =0x55555555
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    cset w0, lo
 ; CHECK-NEXT:    ret
@@ -36,8 +36,8 @@ define i1 @t32_3_2(i32 %X) nounwind {
 define i1 @t32_5_1(i32 %X) nounwind {
 ; CHECK-LABEL: t32_5_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #858993459
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #858993459 // =0x33333333
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
 ; CHECK-NEXT:    cmp w8, w9
@@ -51,11 +51,11 @@ define i1 @t32_5_1(i32 %X) nounwind {
 define i1 @t32_5_2(i32 %X) nounwind {
 ; CHECK-LABEL: t32_5_2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #1717986918
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #1717986918 // =0x66666666
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #858993459
+; CHECK-NEXT:    mov w9, #858993459 // =0x33333333
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    cset w0, lo
 ; CHECK-NEXT:    ret
@@ -67,11 +67,11 @@ define i1 @t32_5_2(i32 %X) nounwind {
 define i1 @t32_5_3(i32 %X) nounwind {
 ; CHECK-LABEL: t32_5_3:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #-1717986919
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #-1717986919 // =0x99999999
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #858993459
+; CHECK-NEXT:    mov w9, #858993459 // =0x33333333
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    cset w0, lo
 ; CHECK-NEXT:    ret
@@ -83,11 +83,11 @@ define i1 @t32_5_3(i32 %X) nounwind {
 define i1 @t32_5_4(i32 %X) nounwind {
 ; CHECK-LABEL: t32_5_4:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #-858993460
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #-858993460 // =0xcccccccc
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #858993459
+; CHECK-NEXT:    mov w9, #858993459 // =0x33333333
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    cset w0, lo
 ; CHECK-NEXT:    ret
@@ -100,11 +100,11 @@ define i1 @t32_5_4(i32 %X) nounwind {
 define i1 @t32_6_1(i32 %X) nounwind {
 ; CHECK-LABEL: t32_6_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
-; CHECK-NEXT:    mov w9, #1431655765
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
+; CHECK-NEXT:    mov w9, #1431655765 // =0x55555555
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #43691
+; CHECK-NEXT:    mov w9, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w9, #10922, lsl #16
 ; CHECK-NEXT:    ror w8, w8, #1
 ; CHECK-NEXT:    cmp w8, w9
@@ -118,11 +118,11 @@ define i1 @t32_6_1(i32 %X) nounwind {
 define i1 @t32_6_2(i32 %X) nounwind {
 ; CHECK-LABEL: t32_6_2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
-; CHECK-NEXT:    mov w9, #-1431655766
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
+; CHECK-NEXT:    mov w9, #-1431655766 // =0xaaaaaaaa
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #43691
+; CHECK-NEXT:    mov w9, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w9, #10922, lsl #16
 ; CHECK-NEXT:    ror w8, w8, #1
 ; CHECK-NEXT:    cmp w8, w9
@@ -136,11 +136,11 @@ define i1 @t32_6_2(i32 %X) nounwind {
 define i1 @t32_6_3(i32 %X) nounwind {
 ; CHECK-LABEL: t32_6_3:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
-; CHECK-NEXT:    mov w9, #-1
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
+; CHECK-NEXT:    mov w9, #-1 // =0xffffffff
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #43691
+; CHECK-NEXT:    mov w9, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w9, #10922, lsl #16
 ; CHECK-NEXT:    ror w8, w8, #1
 ; CHECK-NEXT:    cmp w8, w9
@@ -154,11 +154,11 @@ define i1 @t32_6_3(i32 %X) nounwind {
 define i1 @t32_6_4(i32 %X) nounwind {
 ; CHECK-LABEL: t32_6_4:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    sub w9, w0, #4
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    mul w8, w9, w8
-; CHECK-NEXT:    mov w9, #43690
+; CHECK-NEXT:    mov w9, #43690 // =0xaaaa
 ; CHECK-NEXT:    movk w9, #10922, lsl #16
 ; CHECK-NEXT:    ror w8, w8, #1
 ; CHECK-NEXT:    cmp w8, w9
@@ -172,11 +172,11 @@ define i1 @t32_6_4(i32 %X) nounwind {
 define i1 @t32_6_5(i32 %X) nounwind {
 ; CHECK-LABEL: t32_6_5:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    sub w9, w0, #5
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    mul w8, w9, w8
-; CHECK-NEXT:    mov w9, #43690
+; CHECK-NEXT:    mov w9, #43690 // =0xaaaa
 ; CHECK-NEXT:    movk w9, #10922, lsl #16
 ; CHECK-NEXT:    ror w8, w8, #1
 ; CHECK-NEXT:    cmp w8, w9
@@ -193,10 +193,10 @@ define i1 @t32_6_5(i32 %X) nounwind {
 define i1 @t16_3_2(i16 %X) nounwind {
 ; CHECK-LABEL: t16_3_2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-21845
-; CHECK-NEXT:    mov w9, #-21846
+; CHECK-NEXT:    mov w8, #-21845 // =0xffffaaab
+; CHECK-NEXT:    mov w9, #-21846 // =0xffffaaaa
 ; CHECK-NEXT:    madd w8, w0, w8, w9
-; CHECK-NEXT:    mov w9, #21845
+; CHECK-NEXT:    mov w9, #21845 // =0x5555
 ; CHECK-NEXT:    cmp w9, w8, uxth
 ; CHECK-NEXT:    cset w0, hi
 ; CHECK-NEXT:    ret
@@ -208,8 +208,8 @@ define i1 @t16_3_2(i16 %X) nounwind {
 define i1 @t8_3_2(i8 %X) nounwind {
 ; CHECK-LABEL: t8_3_2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-85
-; CHECK-NEXT:    mov w9, #-86
+; CHECK-NEXT:    mov w8, #-85 // =0xffffffab
+; CHECK-NEXT:    mov w9, #-86 // =0xffffffaa
 ; CHECK-NEXT:    madd w8, w0, w8, w9
 ; CHECK-NEXT:    and w8, w8, #0xff
 ; CHECK-NEXT:    cmp w8, #85
@@ -223,11 +223,11 @@ define i1 @t8_3_2(i8 %X) nounwind {
 define i1 @t64_3_2(i64 %X) nounwind {
 ; CHECK-LABEL: t64_3_2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-6148914691236517206
-; CHECK-NEXT:    mov x9, #-6148914691236517206
+; CHECK-NEXT:    mov x8, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa
+; CHECK-NEXT:    mov x9, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa
 ; CHECK-NEXT:    movk x8, #43691
 ; CHECK-NEXT:    madd x8, x0, x8, x9
-; CHECK-NEXT:    mov x9, #6148914691236517205
+; CHECK-NEXT:    mov x9, #6148914691236517205 // =0x5555555555555555
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    cset w0, lo
 ; CHECK-NEXT:    ret

diff  --git a/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll b/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
index 844921b35466a8..45726e92463b97 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
@@ -4,12 +4,12 @@
 define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
 ; CHECK-LABEL: test_minsize:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5
-; CHECK-NEXT:    mov w9, #42
+; CHECK-NEXT:    mov w8, #5 // =0x5
+; CHECK-NEXT:    mov w9, #42 // =0x2a
 ; CHECK-NEXT:    udiv w8, w0, w8
 ; CHECK-NEXT:    add w8, w8, w8, lsl #2
 ; CHECK-NEXT:    cmp w0, w8
-; CHECK-NEXT:    mov w8, #-10
+; CHECK-NEXT:    mov w8, #-10 // =0xfffffff6
 ; CHECK-NEXT:    csel w0, w9, w8, eq
 ; CHECK-NEXT:    ret
   %rem = urem i32 %X, 5
@@ -21,14 +21,14 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
 define i32 @test_optsize(i32 %X) optsize nounwind readnone {
 ; CHECK-LABEL: test_optsize:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #13108
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #13108 // =0x3334
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #13107, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    cmp w8, w9
-; CHECK-NEXT:    mov w8, #-10
-; CHECK-NEXT:    mov w9, #42
+; CHECK-NEXT:    mov w8, #-10 // =0xfffffff6
+; CHECK-NEXT:    mov w9, #42 // =0x2a
 ; CHECK-NEXT:    csel w0, w9, w8, lo
 ; CHECK-NEXT:    ret
   %rem = urem i32 %X, 5

diff  --git a/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
index a2a27a1508a19b..45239bcec9dbb7 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
@@ -251,7 +251,7 @@ define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
 define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_urem_odd_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movi v2.4s, #1
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -271,7 +271,7 @@ define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
 define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_urem_even_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28087
+; CHECK-NEXT:    mov w8, #28087 // =0x6db7
 ; CHECK-NEXT:    movk w8, #46811, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #1
 ; CHECK-NEXT:    dup v1.4s, w8

diff  --git a/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll b/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
index a989eaa37c11f7..c2233754b46084 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
@@ -6,7 +6,7 @@ define <4 x i1> @t32_3(<4 x i32> %X) nounwind {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -26,11 +26,11 @@ define <4 x i1> @t32_5(<4 x i32> %X) nounwind {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI1_0
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
-; CHECK-NEXT:    mov w8, #52429
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    dup v1.4s, w8
-; CHECK-NEXT:    mov w8, #13106
+; CHECK-NEXT:    mov w8, #13106 // =0x3332
 ; CHECK-NEXT:    movk w8, #13107, lsl #16
 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -47,11 +47,11 @@ define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI2_0
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    dup v1.4s, w8
-; CHECK-NEXT:    mov w8, #43690
+; CHECK-NEXT:    mov w8, #43690 // =0xaaaa
 ; CHECK-NEXT:    movk w8, #10922, lsl #16
 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    dup v2.4s, w8
@@ -70,7 +70,7 @@ define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: t32_6_part1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
-; CHECK-NEXT:    mov w9, #43691
+; CHECK-NEXT:    mov w9, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w9, #43690, lsl #16
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
 ; CHECK-NEXT:    adrp x8, .LCPI3_1
@@ -94,7 +94,7 @@ define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI4_0
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    dup v1.4s, w8

diff  --git a/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll b/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
index 19c59975d7de9c..a173a606e426bc 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
@@ -5,11 +5,11 @@
 define <4 x i32> @test_urem_odd_25(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_urem_odd_25:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movi v2.4s, #1
 ; CHECK-NEXT:    dup v1.4s, w8
-; CHECK-NEXT:    mov w8, #28835
+; CHECK-NEXT:    mov w8, #28835 // =0x70a3
 ; CHECK-NEXT:    movk w8, #2621, lsl #16
 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    dup v1.4s, w8
@@ -26,11 +26,11 @@ define <4 x i32> @test_urem_odd_25(<4 x i32> %X) nounwind {
 define <4 x i32> @test_urem_even_100(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_urem_even_100:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movi v3.4s, #1
 ; CHECK-NEXT:    dup v1.4s, w8
-; CHECK-NEXT:    mov w8, #23592
+; CHECK-NEXT:    mov w8, #23592 // =0x5c28
 ; CHECK-NEXT:    movk w8, #655, lsl #16
 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    dup v2.4s, w8
@@ -96,7 +96,7 @@ define <4 x i32> @test_urem_even_neg100(<4 x i32> %X) nounwind {
 define <4 x i32> @test_urem_odd_undef1(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_urem_odd_undef1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #34079
+; CHECK-NEXT:    mov w8, #34079 // =0x851f
 ; CHECK-NEXT:    movk w8, #20971, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    umull2 v2.2d, v0.4s, v1.4s
@@ -118,7 +118,7 @@ define <4 x i32> @test_urem_odd_undef1(<4 x i32> %X) nounwind {
 define <4 x i32> @test_urem_even_undef1(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: test_urem_even_undef1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #34079
+; CHECK-NEXT:    mov w8, #34079 // =0x851f
 ; CHECK-NEXT:    movk w8, #20971, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    umull2 v2.2d, v0.4s, v1.4s

diff  --git a/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll b/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
index be08ee4c893bd9..a0936ae6fafee9 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
@@ -20,7 +20,7 @@ define <4 x i1> @t0_all_tautological(<4 x i32> %X) nounwind {
 define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: t1_all_odd_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    adrp x8, .LCPI1_0
@@ -39,7 +39,7 @@ define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
 define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: t1_all_odd_ne:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    adrp x8, .LCPI2_0
@@ -58,7 +58,7 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
 define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
 ; CHECK-LABEL: t2_narrow:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    dup v1.8h, w8
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
 ; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
@@ -76,7 +76,7 @@ define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
 define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
 ; CHECK-LABEL: t3_wide:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-6148914691236517206
+; CHECK-NEXT:    mov x8, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa
 ; CHECK-NEXT:    fmov x9, d0
 ; CHECK-NEXT:    movk x8, #43691
 ; CHECK-NEXT:    mov x10, v0.d[1]

diff  --git a/llvm/test/CodeGen/AArch64/urem-seteq.ll b/llvm/test/CodeGen/AArch64/urem-seteq.ll
index 56b030dcca52ab..df87e60c4f8d53 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq.ll
@@ -8,8 +8,8 @@
 define i32 @test_urem_odd(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_odd:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #13108
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #13108 // =0x3334
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    movk w9, #13107, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
@@ -25,8 +25,8 @@ define i32 @test_urem_odd(i32 %X) nounwind {
 define i32 @test_urem_odd_25(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_odd_25:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
-; CHECK-NEXT:    mov w9, #28836
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
+; CHECK-NEXT:    mov w9, #28836 // =0x70a4
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movk w9, #2621, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
@@ -43,7 +43,7 @@ define i32 @test_urem_odd_25(i32 %X) nounwind {
 define i32 @test_urem_odd_bit30(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_odd_bit30:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #27306, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    cmp w8, #4
@@ -59,7 +59,7 @@ define i32 @test_urem_odd_bit30(i32 %X) nounwind {
 define i32 @test_urem_odd_bit31(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_odd_bit31:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #10922, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    cmp w8, #2
@@ -78,7 +78,7 @@ define i32 @test_urem_odd_bit31(i32 %X) nounwind {
 define i16 @test_urem_even(i16 %X) nounwind {
 ; CHECK-LABEL: test_urem_even:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28087
+; CHECK-NEXT:    mov w8, #28087 // =0x6db7
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    and w9, w8, #0xfffc
 ; CHECK-NEXT:    lsr w9, w9, #1
@@ -96,8 +96,8 @@ define i16 @test_urem_even(i16 %X) nounwind {
 define i32 @test_urem_even_100(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_even_100:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23593
-; CHECK-NEXT:    mov w9, #23593
+; CHECK-NEXT:    mov w8, #23593 // =0x5c29
+; CHECK-NEXT:    mov w9, #23593 // =0x5c29
 ; CHECK-NEXT:    movk w8, #49807, lsl #16
 ; CHECK-NEXT:    movk w9, #655, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
@@ -115,7 +115,7 @@ define i32 @test_urem_even_100(i32 %X) nounwind {
 define i32 @test_urem_even_bit30(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_even_bit30:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #20165
+; CHECK-NEXT:    mov w8, #20165 // =0x4ec5
 ; CHECK-NEXT:    movk w8, #64748, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    ror w8, w8, #3
@@ -132,7 +132,7 @@ define i32 @test_urem_even_bit30(i32 %X) nounwind {
 define i32 @test_urem_even_bit31(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_even_bit31:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #64251
+; CHECK-NEXT:    mov w8, #64251 // =0xfafb
 ; CHECK-NEXT:    movk w8, #47866, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    ror w8, w8, #1
@@ -153,8 +153,8 @@ define i32 @test_urem_even_bit31(i32 %X) nounwind {
 define i32 @test_urem_odd_setne(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_odd_setne:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #52429
-; CHECK-NEXT:    mov w9, #858993459
+; CHECK-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-NEXT:    mov w9, #858993459 // =0x33333333
 ; CHECK-NEXT:    movk w8, #52428, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    cmp w8, w9
@@ -170,7 +170,7 @@ define i32 @test_urem_odd_setne(i32 %X) nounwind {
 define i32 @test_urem_negative_odd(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_negative_odd:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #858993459
+; CHECK-NEXT:    mov w8, #858993459 // =0x33333333
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    cmp w8, #1
 ; CHECK-NEXT:    cset w0, hi
@@ -183,7 +183,7 @@ define i32 @test_urem_negative_odd(i32 %X) nounwind {
 define i32 @test_urem_negative_even(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_negative_even:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #37449
+; CHECK-NEXT:    mov w8, #37449 // =0x9249
 ; CHECK-NEXT:    movk w8, #51492, lsl #16
 ; CHECK-NEXT:    mul w8, w0, w8
 ; CHECK-NEXT:    ror w8, w8, #1
@@ -204,7 +204,7 @@ define i32 @test_urem_negative_even(i32 %X) nounwind {
 define i32 @test_urem_one(i32 %X) nounwind {
 ; CHECK-LABEL: test_urem_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #1
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
   %urem = urem i32 %X, 1
   %cmp = icmp eq i32 %urem, 0


        


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