[PATCH] D156587: Implement vector rotations on AArch64 using shift-insert instructions.

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 8 13:21:47 PDT 2023

efriedma added a comment.

Maybe instead of specifically looking at rotates, it makes sense to try to generically pattern-match `(orr x, (srl, y, C))` using known bits?  We already have code along these lines in tryLowerToSLI(); it should be straightforward to make it more generic.

If that isn't straightforward, we can go with this approach for now; there isn't really anything wrong with it.

> XFAIL the RAX1 pattern matching test for the time being, as this breaks the pattern matching for it.

It should be easy enough to update the pattern, or explicitly handle this case in your new code.

Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:6133
+    uint64_t LaneWidth = VT.getVectorElementType().getFixedSizeInBits();
+    if (Splat.isNegative()) {
+      ShlAmt = (-Splat).zextOrTrunc(32);
Since we're dealing with power-of-two integer sizes here, no need to check for negative shift amounts.  You can just mask the shift amount (`Splat.zextOrTrunc(32) & APInt::getLowBitsSet(32, Log2_32(LaneWidth))`).

  rG LLVM Github Monorepo



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