[PATCH] D157259: [DAG] Add constant SPLAT handling in getNodes SIGN_EXTEND_INREG

[Dave Green via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGde775f264d59: [DAG] Add constant SPLAT handling in getNodes SIGN_EXTEND_INREG (authored by dmgreen).

Changed prior to commit:
  https://reviews.llvm.org/D157259?vs=547568&id=548120#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157259/new/

https://reviews.llvm.org/D157259

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
  llvm/test/CodeGen/AArch64/sve-splat-sext.ll


Index: llvm/test/CodeGen/AArch64/sve-splat-sext.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-splat-sext.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O2 -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 8 x i16> @sext_splat_v8i16_128() {
+; CHECK-LABEL: sext_splat_v8i16_128:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.h, #-128 // =0xffffffffffffff80
+; CHECK-NEXT:    ret
+  %i = insertelement <vscale x 8 x i16> poison, i16 128, i32 0
+  %s = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
+  %a = shl <vscale x 8 x i16> %s, shufflevector (<vscale x 8 x i16> insertelement(<vscale x 8 x i16> undef, i16 8, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer)
+  %b = ashr <vscale x 8 x i16> %a, shufflevector (<vscale x 8 x i16> insertelement(<vscale x 8 x i16> undef, i16 8, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer)
+  ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 8 x i1> @sext_icmp_splat_v8i16_128(<vscale x 8 x i8> %d) {
+; CHECK-LABEL: sext_icmp_splat_v8i16_128:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
+; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, #-1
+; CHECK-NEXT:    ret
+  %i = insertelement <vscale x 8 x i8> poison, i8 128, i32 0
+  %s = shufflevector <vscale x 8 x i8> %i, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
+  %c = icmp ugt <vscale x 8 x i8> %s, %d
+  ret <vscale x 8 x i1> %c
+}
+
+define <vscale x 4 x i1> @sext_icmp_splat_v4i16_128(<vscale x 4 x i8> %d) {
+; CHECK-LABEL: sext_icmp_splat_v4i16_128:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    sxtb z0.s, p0/m, z0.s
+; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, #-1
+; CHECK-NEXT:    ret
+  %i = insertelement <vscale x 4 x i8> poison, i8 128, i32 0
+  %s = shufflevector <vscale x 4 x i8> %i, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
+  %c = icmp ugt <vscale x 4 x i8> %s, %d
+  ret <vscale x 4 x i1> %c
+}
Index: llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
+++ llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
@@ -6,21 +6,17 @@
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    mov w8, #3745 // =0xea1
-; CHECK-NEXT:    movk w8, #16618, lsl #16
 ; CHECK-NEXT:    ld1w { z3.d }, p0/z, [x0]
+; CHECK-NEXT:    movk w8, #16618, lsl #16
 ; CHECK-NEXT:    mov w9, #57344 // =0xe000
-; CHECK-NEXT:    mov z6.d, #1023 // =0x3ff
 ; CHECK-NEXT:    movk w9, #17535, lsl #16
 ; CHECK-NEXT:    mov z4.s, w8
 ; CHECK-NEXT:    fmul z4.s, p0/m, z4.s, z3.s
 ; CHECK-NEXT:    mov z5.s, w9
 ; CHECK-NEXT:    fadd z4.s, p0/m, z4.s, z5.s
-; CHECK-NEXT:    mov z5.d, #0 // =0x0
+; CHECK-NEXT:    mov z5.d, #1023 // =0x3ff
 ; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.s
-; CHECK-NEXT:    sxtw z5.d, p0/m, z5.d
-; CHECK-NEXT:    smax z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT:    movprfx z5, z6
-; CHECK-NEXT:    sxtw z5.d, p0/m, z6.d
+; CHECK-NEXT:    smax z4.d, z4.d, #0
 ; CHECK-NEXT:    smin z4.d, p0/m, z4.d, z5.d
 ; CHECK-NEXT:    cmpne p1.d, p0/z, z4.d, #0
 ; CHECK-NEXT:    ld1w { z4.d }, p1/z, [x1]
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6592,6 +6592,13 @@
       }
       return getBuildVector(VT, DL, Ops);
     }
+
+    if (N1.getOpcode() == ISD::SPLAT_VECTOR &&
+        isa<ConstantSDNode>(N1.getOperand(0)))
+      return getNode(
+          ISD::SPLAT_VECTOR, DL, VT,
+          SignExtendInReg(N1.getConstantOperandAPInt(0),
+                          N1.getOperand(0).getValueType()));
     break;
   }
   case ISD::FP_TO_SINT_SAT:


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