[PATCH] D153848: [RISCV] Apply promotion for f16 vector ops when only have zvfhmin.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan marked 7 inline comments as done.
jacquesguan added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:580
+        Operands[j] =
+            DAG.getNode(ISD::BITCAST, DL, NewVecVT, Node->getOperand(j));
+    else if (Node->getOperand(j).getValueType() == ScalarVT &&
----------------
michaelmaitland wrote:
> Why BITCAST instead of ANY_EXTEND, but for the scalar below we ANY_EXTEND?
Part of this code is from the function `VectorLegalizer::Promote`, so there is some cases such as promote AND v2i32 to v1i64 in x86, so I set bitcast here to keep consistent with  `VectorLegalizer::Promote`. But thanks for your comment, I rethink about the promotion of reduce op. I think there won't be any cases to use BITCAST now, so I rewrite this fucntion.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153848/new/

https://reviews.llvm.org/D153848