[llvm] 30b52a3 - [CSKY] Optimize conditional branch and value select with BTSTI
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 7 23:14:13 PDT 2023
Author: Ben Shi
Date: 2023-08-08T14:13:48+08:00
New Revision: 30b52a35741a0edaacc5c0251e9199c8ad3bdfd7
URL: https://github.com/llvm/llvm-project/commit/30b52a35741a0edaacc5c0251e9199c8ad3bdfd7
DIFF: https://github.com/llvm/llvm-project/commit/30b52a35741a0edaacc5c0251e9199c8ad3bdfd7.diff
LOG: [CSKY] Optimize conditional branch and value select with BTSTI
Reviewed By: zixuan-wu
Differential Revision: https://reviews.llvm.org/D154768
Added:
Modified:
llvm/lib/Target/CSKY/CSKYInstrInfo.td
llvm/test/CodeGen/CSKY/br.ll
llvm/test/CodeGen/CSKY/cmp-i.ll
llvm/test/CodeGen/CSKY/select.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index 2e475d1f1b6d01..c6bfc2495ae29b 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -167,7 +167,7 @@ def imm32_1_pop_bit_XFORM : SDNodeXForm<imm, [{
}]>;
def imm32_1_pop_bit : PatLeaf<(imm), [{
uint32_t I = N->getZExtValue();
- return llvm::popcount(I) == 1 && I > 0xffff;
+ return llvm::popcount(I) == 1 && I > 0xfff;
}]>;
// Optimize (and x, imm) to (BCLRI x, log2(~imm)). We should exclude the
@@ -1202,6 +1202,13 @@ multiclass BTF32Pat0<PatFrag cond0, PatFrag cond1, ImmLeaf imm_ty, Instruction i
defm : BTF32Pat0<setne, seteq, uimm16, CMPNEI32>;
defm : BTF32Pat0<setuge, setult, oimm16, CMPHSI32>;
defm : BTF32Pat0<setlt, setge, oimm16, CMPLTI32>;
+
+def : Pat<(brcond (i32 (setne (and GPR:$rs, imm32_1_pop_bit:$im), 0)), bb:$imm16),
+ (BT32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),
+ bb:$imm16)>;
+def : Pat<(brcond (i32 (seteq (and GPR:$rs, imm32_1_pop_bit:$im), 0)), bb:$imm16),
+ (BF32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),
+ bb:$imm16)>;
}
let Predicates = [iHas2E3] in {
@@ -1250,6 +1257,8 @@ def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 -1))), bb:$imm16),
let Predicates = [iHas2E3] in {
def : Pat<(setne GPR:$rs1, GPR:$rs2),
(CMPNE32 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(setne (and GPR:$rs, imm32_1_pop_bit:$im), 0),
+ (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im))>;
def : Pat<(i32 (seteq GPR:$rs1, GPR:$rs2)),
(MVCV32 (CMPNE32 GPR:$rs1, GPR:$rs2))>;
def : Pat<(setuge GPR:$rs1, GPR:$rs2),
@@ -1366,8 +1375,16 @@ def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
(ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
(ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
-}
+def : Pat<(select (i32 (setne (and GPR:$rs, imm32_1_pop_bit:$im), 0)),
+ GPR:$true, GPR:$false),
+ (MOVT32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),
+ GPR:$true, GPR:$false)>;
+def : Pat<(select (i32 (seteq (and GPR:$rs, imm32_1_pop_bit:$im), 0)),
+ GPR:$true, GPR:$false),
+ (MOVF32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),
+ GPR:$true, GPR:$false)>;
+}
let Predicates = [iHas2E3] in {
def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
diff --git a/llvm/test/CodeGen/CSKY/br.ll b/llvm/test/CodeGen/CSKY/br.ll
index ccd26f6229e5cb..d3ca7ef22a7b35 100644
--- a/llvm/test/CodeGen/CSKY/br.ll
+++ b/llvm/test/CodeGen/CSKY/br.ll
@@ -6615,9 +6615,8 @@ label2:
define i32 @br_bit_test_eq_0(i32 %c) {
; CHECK-LABEL: br_bit_test_eq_0:
; CHECK: # %bb.0:
-; CHECK-NEXT: movih32 a1, 2
-; CHECK-NEXT: and16 a0, a1
-; CHECK-NEXT: bnez32 a0, .LBB145_2
+; CHECK-NEXT: btsti16 a0, 17
+; CHECK-NEXT: bt32 .LBB145_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
@@ -6661,9 +6660,8 @@ label2:
define i32 @br_bit_test_ne_0(i32 %c) {
; CHECK-LABEL: br_bit_test_ne_0:
; CHECK: # %bb.0:
-; CHECK-NEXT: movih32 a1, 2
-; CHECK-NEXT: and16 a0, a1
-; CHECK-NEXT: bez32 a0, .LBB146_2
+; CHECK-NEXT: btsti16 a0, 17
+; CHECK-NEXT: bf32 .LBB146_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
@@ -6707,9 +6705,8 @@ label2:
define i32 @br_bit_test_eq_mask(i32 %c) {
; CHECK-LABEL: br_bit_test_eq_mask:
; CHECK: # %bb.0:
-; CHECK-NEXT: movih32 a1, 2
-; CHECK-NEXT: and16 a0, a1
-; CHECK-NEXT: bez32 a0, .LBB147_2
+; CHECK-NEXT: btsti16 a0, 17
+; CHECK-NEXT: bf32 .LBB147_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
@@ -6753,9 +6750,8 @@ label2:
define i32 @br_bit_test_ne_mask(i32 %c) {
; CHECK-LABEL: br_bit_test_ne_mask:
; CHECK: # %bb.0:
-; CHECK-NEXT: movih32 a1, 2
-; CHECK-NEXT: and16 a0, a1
-; CHECK-NEXT: bnez32 a0, .LBB148_2
+; CHECK-NEXT: btsti16 a0, 17
+; CHECK-NEXT: bt32 .LBB148_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
diff --git a/llvm/test/CodeGen/CSKY/cmp-i.ll b/llvm/test/CodeGen/CSKY/cmp-i.ll
index ceb78aba6fc739..38642d4f9de98e 100644
--- a/llvm/test/CodeGen/CSKY/cmp-i.ll
+++ b/llvm/test/CodeGen/CSKY/cmp-i.ll
@@ -78,6 +78,39 @@ entry:
ret i1 %icmp
}
+define i1 @icmpRI_AND_ne(i32 %x) {
+; CHECK-LABEL: icmpRI_AND_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti16 a0, 15
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+;
+; GENERIC-LABEL: icmpRI_AND_ne:
+; GENERIC: # %bb.0: # %entry
+; GENERIC-NEXT: .cfi_def_cfa_offset 0
+; GENERIC-NEXT: subi16 sp, sp, 4
+; GENERIC-NEXT: .cfi_def_cfa_offset 4
+; GENERIC-NEXT: movi16 a1, 0
+; GENERIC-NEXT: lsli16 a2, a1, 24
+; GENERIC-NEXT: lsli16 a3, a1, 16
+; GENERIC-NEXT: or16 a3, a2
+; GENERIC-NEXT: movi16 a2, 128
+; GENERIC-NEXT: lsli16 a2, a2, 8
+; GENERIC-NEXT: or16 a2, a3
+; GENERIC-NEXT: or16 a2, a1
+; GENERIC-NEXT: and16 a2, a0
+; GENERIC-NEXT: cmpnei16 a2, 0
+; GENERIC-NEXT: mvcv16 a1
+; GENERIC-NEXT: movi16 a0, 1
+; GENERIC-NEXT: subu16 a0, a1
+; GENERIC-NEXT: addi16 sp, sp, 4
+; GENERIC-NEXT: rts16
+entry:
+ %and = and i32 %x, 32768
+ %icmp = icmp ne i32 %and, 0
+ ret i1 %icmp
+}
+
define i1 @ICMP_LONG_eq(i64 %x, i64 %y) {
; CHECK-LABEL: ICMP_LONG_eq:
; CHECK: # %bb.0: # %entry
@@ -708,10 +741,10 @@ define i1 @ICMP_LONG_ugt(i64 %x, i64 %y) {
; GENERIC-NEXT: cmpne16 a3, a1
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB25_2
+; GENERIC-NEXT: bt16 .LBB26_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: mov16 a0, l0
-; GENERIC-NEXT: .LBB25_2: # %entry
+; GENERIC-NEXT: .LBB26_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
; GENERIC-NEXT: addi16 sp, sp, 4
@@ -743,11 +776,11 @@ define i1 @ICMP_LONG_I_ugt(i64 %x) {
; GENERIC-NEXT: cmphs16 a2, a0
; GENERIC-NEXT: mvcv16 a0
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB26_2
+; GENERIC-NEXT: bt16 .LBB27_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: subu16 a2, a1
; GENERIC-NEXT: mov16 a0, a2
-; GENERIC-NEXT: .LBB26_2: # %entry
+; GENERIC-NEXT: .LBB27_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
entry:
@@ -1046,13 +1079,13 @@ define i1 @ICMP_LONG_uge(i64 %x, i64 %y) {
; GENERIC-NEXT: cmpne16 a3, a1
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB36_2
+; GENERIC-NEXT: bt16 .LBB37_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: subu16 a0, l1
-; GENERIC-NEXT: br32 .LBB36_3
-; GENERIC-NEXT: .LBB36_2:
+; GENERIC-NEXT: br32 .LBB37_3
+; GENERIC-NEXT: .LBB37_2:
; GENERIC-NEXT: subu16 a0, a2
-; GENERIC-NEXT: .LBB36_3: # %entry
+; GENERIC-NEXT: .LBB37_3: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
; GENERIC-NEXT: ld16.w l1, (sp, 4) # 4-byte Folded Reload
@@ -1366,10 +1399,10 @@ define i1 @ICMP_LONG_ult(i64 %x, i64 %y) {
; GENERIC-NEXT: cmpne16 a3, a1
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB47_2
+; GENERIC-NEXT: bt16 .LBB48_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: mov16 a0, l0
-; GENERIC-NEXT: .LBB47_2: # %entry
+; GENERIC-NEXT: .LBB48_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
; GENERIC-NEXT: addi16 sp, sp, 4
@@ -1688,13 +1721,13 @@ define i1 @ICMP_LONG_ule(i64 %x, i64 %y) {
; GENERIC-NEXT: cmpne16 a3, a1
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB58_2
+; GENERIC-NEXT: bt16 .LBB59_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: subu16 a0, l1
-; GENERIC-NEXT: br32 .LBB58_3
-; GENERIC-NEXT: .LBB58_2:
+; GENERIC-NEXT: br32 .LBB59_3
+; GENERIC-NEXT: .LBB59_2:
; GENERIC-NEXT: subu16 a0, a2
-; GENERIC-NEXT: .LBB58_3: # %entry
+; GENERIC-NEXT: .LBB59_3: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
; GENERIC-NEXT: ld16.w l1, (sp, 4) # 4-byte Folded Reload
@@ -1733,10 +1766,10 @@ define i1 @ICMP_LONG_I_ule(i64 %x) {
; GENERIC-NEXT: cmpnei16 a1, 0
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB59_2
+; GENERIC-NEXT: bt16 .LBB60_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: movi16 a0, 0
-; GENERIC-NEXT: .LBB59_2: # %entry
+; GENERIC-NEXT: .LBB60_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
entry:
@@ -2030,11 +2063,11 @@ define i1 @ICMP_LONG_sgt(i64 %x, i64 %y) {
; GENERIC-NEXT: cmpne16 a3, a1
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB69_2
+; GENERIC-NEXT: bt16 .LBB70_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: subu16 a0, l0
-; GENERIC-NEXT: .LBB69_2: # %entry
+; GENERIC-NEXT: .LBB70_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
; GENERIC-NEXT: addi16 sp, sp, 4
@@ -2083,11 +2116,11 @@ define i1 @ICMP_LONG_I_sgt(i64 %x) {
; GENERIC-NEXT: cmpnei16 a1, 0
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB70_2
+; GENERIC-NEXT: bt16 .LBB71_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: subu16 a3, a2
; GENERIC-NEXT: mov16 a0, a3
-; GENERIC-NEXT: .LBB70_2: # %entry
+; GENERIC-NEXT: .LBB71_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
entry:
@@ -2360,11 +2393,11 @@ define i1 @ICMP_LONG_sge(i64 %x, i64 %y) {
; GENERIC-NEXT: cmpne16 a3, a1
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bf16 .LBB80_2
+; GENERIC-NEXT: bf16 .LBB81_2
; GENERIC-NEXT: # %bb.1:
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: subu16 a0, a2
-; GENERIC-NEXT: .LBB80_2: # %entry
+; GENERIC-NEXT: .LBB81_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
entry:
@@ -2415,12 +2448,12 @@ define i1 @ICMP_LONG_I_sge(i64 %x) {
; GENERIC-NEXT: cmpnei16 a1, 0
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB81_2
+; GENERIC-NEXT: bt16 .LBB82_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: subu16 a0, a3
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
-; GENERIC-NEXT: .LBB81_2:
+; GENERIC-NEXT: .LBB82_2:
; GENERIC-NEXT: subu16 a0, a2
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
@@ -2694,11 +2727,11 @@ define i1 @ICMP_LONG_slt(i64 %x, i64 %y) {
; GENERIC-NEXT: cmpne16 a3, a1
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB91_2
+; GENERIC-NEXT: bt16 .LBB92_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: subu16 a0, l0
-; GENERIC-NEXT: .LBB91_2: # %entry
+; GENERIC-NEXT: .LBB92_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
; GENERIC-NEXT: addi16 sp, sp, 4
@@ -2745,11 +2778,11 @@ define i1 @ICMP_LONG_I_slt(i64 %x) {
; GENERIC-NEXT: cmpnei16 a1, 0
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB92_2
+; GENERIC-NEXT: bt16 .LBB93_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: subu16 a0, a2
-; GENERIC-NEXT: .LBB92_2: # %entry
+; GENERIC-NEXT: .LBB93_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
entry:
@@ -3018,11 +3051,11 @@ define i1 @ICMP_LONG_sle(i64 %x, i64 %y) {
; GENERIC-NEXT: cmpne16 a3, a1
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bf16 .LBB102_2
+; GENERIC-NEXT: bf16 .LBB103_2
; GENERIC-NEXT: # %bb.1:
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: subu16 a0, a2
-; GENERIC-NEXT: .LBB102_2: # %entry
+; GENERIC-NEXT: .LBB103_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
entry:
@@ -3067,11 +3100,11 @@ define i1 @ICMP_LONG_I_sle(i64 %x) {
; GENERIC-NEXT: cmpnei16 a1, 0
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: btsti16 a1, 0
-; GENERIC-NEXT: bt16 .LBB103_2
+; GENERIC-NEXT: bt16 .LBB104_2
; GENERIC-NEXT: # %bb.1: # %entry
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: subu16 a0, a2
-; GENERIC-NEXT: .LBB103_2: # %entry
+; GENERIC-NEXT: .LBB104_2: # %entry
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
entry:
diff --git a/llvm/test/CodeGen/CSKY/select.ll b/llvm/test/CodeGen/CSKY/select.ll
index b0f1165bde2861..65488850d4bab9 100644
--- a/llvm/test/CodeGen/CSKY/select.ll
+++ b/llvm/test/CodeGen/CSKY/select.ll
@@ -8163,9 +8163,7 @@ entry:
define i32 @select_bit_test_eq_0(i32 %0) {
; CHECK-LABEL: select_bit_test_eq_0:
; CHECK: # %bb.0:
-; CHECK-NEXT: movih32 a1, 2
-; CHECK-NEXT: and16 a0, a1
-; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: btsti16 a0, 17
; CHECK-NEXT: movi16 a0, 23
; CHECK-NEXT: movi16 a1, 1
; CHECK-NEXT: movf32 a0, a1
@@ -8204,9 +8202,7 @@ define i32 @select_bit_test_eq_0(i32 %0) {
define i32 @select_bit_test_ne_0(i32 %0) {
; CHECK-LABEL: select_bit_test_ne_0:
; CHECK: # %bb.0:
-; CHECK-NEXT: movih32 a1, 2
-; CHECK-NEXT: and16 a0, a1
-; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: btsti16 a0, 17
; CHECK-NEXT: movi16 a0, 34
; CHECK-NEXT: movi16 a1, 5
; CHECK-NEXT: movt32 a0, a1
@@ -8247,9 +8243,7 @@ define i32 @select_bit_test_ne_0(i32 %0) {
define i32 @select_bit_test_eq_mask(i32 %0) {
; CHECK-LABEL: select_bit_test_eq_mask:
; CHECK: # %bb.0:
-; CHECK-NEXT: movih32 a1, 2
-; CHECK-NEXT: and16 a0, a1
-; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: btsti16 a0, 17
; CHECK-NEXT: movi16 a0, 5
; CHECK-NEXT: movi16 a1, 34
; CHECK-NEXT: movt32 a0, a1
@@ -8290,9 +8284,7 @@ define i32 @select_bit_test_eq_mask(i32 %0) {
define i32 @select_bit_test_ne_mask(i32 %0) {
; CHECK-LABEL: select_bit_test_ne_mask:
; CHECK: # %bb.0:
-; CHECK-NEXT: movih32 a1, 2
-; CHECK-NEXT: and16 a0, a1
-; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: btsti16 a0, 17
; CHECK-NEXT: movi16 a0, 34
; CHECK-NEXT: movi16 a1, 5
; CHECK-NEXT: movt32 a0, a1
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