[PATCH] D157113: [AArch64] Support more types for ZEXT/SEXT with Global Isel

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h:1046-1070
         if (ConvertOp) {
-          LLT MergeSrcTy = MRI.getType(MergeI->getOperand(1).getReg());
+          LLT MergeDstTy = MRI.getType(SrcDef->getOperand(0).getReg());
 
           // This is a vector that is being split and casted. Extract to the
           // element type, and do the conversion on the scalars (or smaller
           // vectors).
+          LLT MergeEltTy = MergeDstTy.divide(NumMergeRegs);
----------------
Is it possible to separate this from the lowerEXT parts?


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:5981
+    // zext x -> zext(merge(zext(unmerge), zext(unmerge)))
+    if (LI.getAction({MI.getOpcode(), {MidTy, SrcTy}}).Action == Legal) {
+      Register MidRegister = MRI.createGenericVirtualRegister(MidTy);
----------------
This shouldn't need to consider the legality of intermediate ops and fail, just unconditionally do this and let the new artifacts legalize


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157113/new/

https://reviews.llvm.org/D157113