[PATCH] D99750: [LV, VP]VP intrinsics support for the Loop Vectorizer

[Kolya Panchenko via Phabricator via llvm-commits]

nikolaypanchenko added inline comments.


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Comment at: llvm/lib/Transforms/Vectorize/VPlan.h:2065
+/// for current tail-folding implementation.
+/// 2. The second way is to insert instructions to compute min(VF, trip_count -
+/// index) for each vector iteration.
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ABataev wrote:
> fhahn wrote:
> > ABataev wrote:
> > > fhahn wrote:
> > > > ABataev wrote:
> > > > > fhahn wrote:
> > > > > > IIUC this is what the recipe actually computes at the moment, right?
> > > > > No, currently it emits number 3. Other are not fully supported, they will require some extra work.
> > > > Ah I see, would be good to update
> > > Will update the comment
> > Thanks for the update! IIUC options 1) and 2) don't need to be handled by `VPEVLRecipe`, 1) would just be a live-in VPValue and 2) could be a set VPInsructions to compute it. Would it make sense to only focus on 3) for EVL recipe.
> > 
> > It would be good to mention that the recipe effectively sets the EVL for the remainder of the region.
> 1. Will remove 1 and 2 and will focus only on 3.
> 2. It is not quite correct. For RISC-V it may return different values (< VLMAX) for 2 last iterations, not only for the remainder.
To second @ABataev comment on 2): VL csr is controlled by `vset*vl*` instruction that has following behavior https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#63-constraints-on-setting-vl. Being more precise, with VLMAX=8 and AVL=9, it may either do (8, 1) or (5, 4).


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