[PATCH] D157279: [CodeGen] Disable FP LD1RX instructions generation for Neoverse-V1

Mon Aug 7 07:59:33 PDT 2023

igor.kirillov marked an inline comment as done.
igor.kirillov added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64.td:151

+def FeatureAvoidLD1R : SubtargetFeature<"avoid-ld1r",
+  "AvoidLD1R", "true", "Prefer LDR(LDP)+MOV ove LD1RX">;
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paulwalker-arm wrote:
> This doesn't accurately represent the "feature" you want to model.
> 
> Firstly the effect is specific to SVE rather than wanting to avoid all uses of ld1r (plus below I reason that we also might want to keep the integer variants as is).
> 
> Secondly the issue is that on Neoverse V1 there are fewer LS pipelines for SVE than NEON.  This is not normally a problem because the SVE registers are twice the size of NEON and so the overall bandwidth is greater.  However, when loading 128-bit or smaller datatypes the bandwidth switches in favour of NEON with its extra LS pipe. (Noting that on V1 the latency of LD1R is the same are LDR+DUP)
> 
> The choice is yours but as a minimum, and based on agreement regarding the integer variants, I'd be happy with "sve-avoid-fp-ld1r" but if there's a nice way to sum up the second point above then that'll be perfect.
I've decided to use `no-` prefix rather than `avoid` as it seems to be the way it is done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157279/new/

https://reviews.llvm.org/D157279