[PATCH] D157287: [LegalizeTypes][RISCV] Correct FP_TO_{S,U}INT expansion when bf16 isn't a legal type

[Alex Bradbury via Phabricator via llvm-commits]

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As noted in D156990 <https://reviews.llvm.org/D156990>, the logic in ExpandIntRes_FP_TO_SINT assumes that if the type action for the float type is TypeSoftPromoteHalf, is must have been an f16 (half).  However, that type action has been overloaded and is used for both f16 and bf16. This patch adds an appropriate check to ensure ISD::FP16_TO_FP or ISD::BF16_TO_FP is emitted as required.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157287

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/RISCV/bfloat-convert.ll


Index: llvm/test/CodeGen/RISCV/bfloat-convert.ll
===================================================================
--- llvm/test/CodeGen/RISCV/bfloat-convert.ll
+++ llvm/test/CodeGen/RISCV/bfloat-convert.ll
@@ -449,7 +449,9 @@
 ; RV32ID:       # %bb.0:
 ; RV32ID-NEXT:    addi sp, sp, -16
 ; RV32ID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32ID-NEXT:    call __extendhfsf2 at plt
+; RV32ID-NEXT:    fmv.x.w a0, fa0
+; RV32ID-NEXT:    slli a0, a0, 16
+; RV32ID-NEXT:    fmv.w.x fa0, a0
 ; RV32ID-NEXT:    call __fixsfdi at plt
 ; RV32ID-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32ID-NEXT:    addi sp, sp, 16
@@ -641,7 +643,9 @@
 ; RV32ID:       # %bb.0:
 ; RV32ID-NEXT:    addi sp, sp, -16
 ; RV32ID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32ID-NEXT:    call __extendhfsf2 at plt
+; RV32ID-NEXT:    fmv.x.w a0, fa0
+; RV32ID-NEXT:    slli a0, a0, 16
+; RV32ID-NEXT:    fmv.w.x fa0, a0
 ; RV32ID-NEXT:    call __fixunssfdi at plt
 ; RV32ID-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32ID-NEXT:    addi sp, sp, 16
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -3616,7 +3616,9 @@
   if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
     EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
     Op = GetSoftPromotedHalf(Op);
-    Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
+    Op = DAG.getNode(Op.getValueType() == MVT::f16 ? ISD::FP16_TO_FP
+                                                   : ISD::BF16_TO_FP,
+                     dl, NFPVT, Op);
     Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
     SplitInteger(Op, Lo, Hi);
     return;
@@ -3653,7 +3655,9 @@
   if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
     EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
     Op = GetSoftPromotedHalf(Op);
-    Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
+    Op = DAG.getNode(Op.getValueType() == MVT::f16 ? ISD::FP16_TO_FP
+                                                   : ISD::BF16_TO_FP,
+                     dl, NFPVT, Op);
     Op = DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op);
     SplitInteger(Op, Lo, Hi);
     return;


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