[llvm] e61ca23 - [AMDGPU] Add and use SIInstrFlags::GWS. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 7 04:05:31 PDT 2023
Author: Jay Foad
Date: 2023-08-07T12:05:14+01:00
New Revision: e61ca23289393bd0dae65c589daadb40518eb1b9
URL: https://github.com/llvm/llvm-project/commit/e61ca23289393bd0dae65c589daadb40518eb1b9
DIFF: https://github.com/llvm/llvm-project/commit/e61ca23289393bd0dae65c589daadb40518eb1b9.diff
LOG: [AMDGPU] Add and use SIInstrFlags::GWS. NFC.
This reduces the number of places where we have to check for a list of
DS_GWS_* opcodes.
Differential Revision: https://reviews.llvm.org/D157099
Added:
Modified:
llvm/lib/Target/AMDGPU/DSInstructions.td
llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
llvm/lib/Target/AMDGPU/SIInstrFormats.td
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 90a656ad50b463..c8c87c5a943e30 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -12,6 +12,7 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
let LGKM_CNT = 1;
let DS = 1;
+ let GWS = 0;
let Size = 8;
let UseNamedOperandTable = 1;
@@ -61,6 +62,7 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
let UseNamedOperandTable = 1;
// copy relevant pseudo op flags
+ let GWS = ps.GWS;
let SubtargetPredicate = ps.SubtargetPredicate;
let OtherPredicates = ps.OtherPredicates;
let SchedRW = ps.SchedRW;
@@ -376,6 +378,7 @@ multiclass DS_1A_mc <string opName> {
class DS_GWS <string opName, dag ins, string asmOps>
: DS_Pseudo<opName, (outs), ins, asmOps> {
+ let GWS = 1;
let has_vdst = 0;
let has_addr = 0;
diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
index a1f8be403c441f..cbe1206e649825 100644
--- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
+++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
@@ -317,13 +317,15 @@ bool AMDGPUCustomBehaviour::hasModifiersSet(
return true;
}
+// taken from SIInstrInfo::isGWS()
+bool AMDGPUCustomBehaviour::isGWS(uint16_t Opcode) const {
+ const MCInstrDesc &MCID = MCII.get(Opcode);
+ return MCID.TSFlags & SIInstrFlags::GWS;
+}
+
// taken from SIInstrInfo::isAlwaysGDS()
bool AMDGPUCustomBehaviour::isAlwaysGDS(uint16_t Opcode) const {
- return Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::DS_GWS_INIT ||
- Opcode == AMDGPU::DS_GWS_SEMA_V || Opcode == AMDGPU::DS_GWS_SEMA_BR ||
- Opcode == AMDGPU::DS_GWS_SEMA_P ||
- Opcode == AMDGPU::DS_GWS_SEMA_RELEASE_ALL ||
- Opcode == AMDGPU::DS_GWS_BARRIER;
+ return Opcode == AMDGPU::DS_ORDERED_COUNT || isGWS(Opcode);
}
} // namespace mca
diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
index cb1436d319c978..3a231758887ba6 100644
--- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
+++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
@@ -68,6 +68,8 @@ class AMDGPUCustomBehaviour : public CustomBehaviour {
bool hasModifiersSet(const std::unique_ptr<Instruction> &Inst,
unsigned OpName) const;
/// Helper function used in generateWaitCntInfo()
+ bool isGWS(uint16_t Opcode) const;
+ /// Helper function used in generateWaitCntInfo()
bool isAlwaysGDS(uint16_t Opcode) const;
/// Helper function used in generateWaitCntInfo()
bool isVMEM(const MCInstrDesc &MCID);
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index cd1818285e3eb0..7d0309e435b059 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -161,6 +161,9 @@ enum : uint64_t {
// Is never uniform.
IsNeverUniform = UINT64_C(1) << 61,
+
+ // ds_gws_* instructions.
+ GWS = UINT64_C(1) << 62,
};
// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 4b0283b27a6f5c..bda7743a089155 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -588,12 +588,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
AMDGPU::OpName::data1),
CurrScore);
}
- } else if (SIInstrInfo::isAtomicRet(Inst) &&
- Inst.getOpcode() != AMDGPU::DS_GWS_INIT &&
- Inst.getOpcode() != AMDGPU::DS_GWS_SEMA_V &&
- Inst.getOpcode() != AMDGPU::DS_GWS_SEMA_BR &&
- Inst.getOpcode() != AMDGPU::DS_GWS_SEMA_P &&
- Inst.getOpcode() != AMDGPU::DS_GWS_BARRIER &&
+ } else if (SIInstrInfo::isAtomicRet(Inst) && !SIInstrInfo::isGWS(Inst) &&
Inst.getOpcode() != AMDGPU::DS_APPEND &&
Inst.getOpcode() != AMDGPU::DS_CONSUME &&
Inst.getOpcode() != AMDGPU::DS_ORDERED_COUNT) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index f674777724ebbb..7dccb6025facdb 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -156,6 +156,9 @@ class InstSI <dag outs, dag ins, string asm = "",
// This bit indicates that the instruction is never-uniform/divergent
field bit IsNeverUniform = 0;
+ // ds_gws_* instructions.
+ field bit GWS = 0;
+
// These need to be kept in sync with the enum in SIInstrFlags.
let TSFlags{0} = SALU;
let TSFlags{1} = VALU;
@@ -239,6 +242,8 @@ class InstSI <dag outs, dag ins, string asm = "",
let TSFlags{61} = IsNeverUniform;
+ let TSFlags{62} = GWS;
+
let SchedRW = [Write32Bit];
let AsmVariantName = AMDGPUAsmVariants.Default;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 8b902aeda56119..393d54747cb1d0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3732,13 +3732,7 @@ bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
}
bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
- return Opcode == AMDGPU::DS_ORDERED_COUNT ||
- Opcode == AMDGPU::DS_GWS_INIT ||
- Opcode == AMDGPU::DS_GWS_SEMA_V ||
- Opcode == AMDGPU::DS_GWS_SEMA_BR ||
- Opcode == AMDGPU::DS_GWS_SEMA_P ||
- Opcode == AMDGPU::DS_GWS_SEMA_RELEASE_ALL ||
- Opcode == AMDGPU::DS_GWS_BARRIER;
+ return Opcode == AMDGPU::DS_ORDERED_COUNT || isGWS(Opcode);
}
bool SIInstrInfo::modifiesModeRegister(const MachineInstr &MI) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index b25aae7b2fb043..d42f2ab46168c4 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -531,6 +531,14 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return get(Opcode).TSFlags & SIInstrFlags::DS;
}
+ static bool isGWS(const MachineInstr &MI) {
+ return MI.getDesc().TSFlags & SIInstrFlags::GWS;
+ }
+
+ bool isGWS(uint16_t Opcode) const {
+ return get(Opcode).TSFlags & SIInstrFlags::GWS;
+ }
+
bool isAlwaysGDS(uint16_t Opcode) const;
static bool isMIMG(const MachineInstr &MI) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 304cdcc825aa4a..5859f978e890e3 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2000,6 +2000,10 @@ bool hasPackedD16(const MCSubtargetInfo &STI) {
!isSI(STI);
}
+bool hasGDS(const MCSubtargetInfo &STI) {
+ return STI.hasFeature(AMDGPU::FeatureGDS);
+}
+
unsigned getNSAMaxSize(const MCSubtargetInfo &STI) {
auto Version = getIsaVersion(STI.getCPU());
if (Version.Major == 10)
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index b30b1faf7e499a..69236fba6e4cb5 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1140,6 +1140,7 @@ bool hasMIMG_R128(const MCSubtargetInfo &STI);
bool hasA16(const MCSubtargetInfo &STI);
bool hasG16(const MCSubtargetInfo &STI);
bool hasPackedD16(const MCSubtargetInfo &STI);
+bool hasGDS(const MCSubtargetInfo &STI);
unsigned getNSAMaxSize(const MCSubtargetInfo &STI);
bool isSI(const MCSubtargetInfo &STI);
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