[PATCH] D157089: [AMDGPU] Fix dealing with register interval endpoints in SIInsertWaitcnts.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev added a comment.

> Is this NFC? So long as the two pieces of code you updated are consistent, there is no bug, is there?

What is the SGPR interval change consistent with?

For VGPRs, I guess seeing it an NFC rather than a couple bugs masking one another would imply being fine with different instances of the same type having different invariants or maybe disregarding the conceptual dimension of it all whatsoever, if this is a better crime.


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https://reviews.llvm.org/D157089