[PATCH] D157259: [DAG] Add constant SPLAT handling in getNodes SIGN_EXTEND_INREG

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: RKSimon, craig.topper, reames, sdesmalen.
Herald added subscribers: steven.zhang, hiraditya.
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dmgreen requested review of this revision.
Herald added a subscriber: wangpc.
Herald added a project: LLVM.

This helps simplify constant splats a little. Without this the code in https://github.com/llvm/llvm-project/blob/b8e297d1af5ae42e81b4c79e14a6d2427db0311b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L14072 always returns the existing node.


https://reviews.llvm.org/D157259

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
  llvm/test/CodeGen/AArch64/sve-splat-sext.ll


Index: llvm/test/CodeGen/AArch64/sve-splat-sext.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-splat-sext.ll
+++ llvm/test/CodeGen/AArch64/sve-splat-sext.ll
@@ -17,10 +17,8 @@
 ; CHECK-LABEL: sext_icmp_splat_v8i16_128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z1.h, #255 // =0xff
 ; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
-; CHECK-NEXT:    sxtb z1.h, p0/m, z1.h
-; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, z1.h
+; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, #-1
 ; CHECK-NEXT:    ret
   %i = insertelement <vscale x 8 x i8> poison, i8 128, i32 0
   %s = shufflevector <vscale x 8 x i8> %i, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -32,10 +30,8 @@
 ; CHECK-LABEL: sext_icmp_splat_v4i16_128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z1.s, #255 // =0xff
 ; CHECK-NEXT:    sxtb z0.s, p0/m, z0.s
-; CHECK-NEXT:    sxtb z1.s, p0/m, z1.s
-; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, #-1
 ; CHECK-NEXT:    ret
   %i = insertelement <vscale x 4 x i8> poison, i8 128, i32 0
   %s = shufflevector <vscale x 4 x i8> %i, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
Index: llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
+++ llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
@@ -6,21 +6,17 @@
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    mov w8, #3745 // =0xea1
-; CHECK-NEXT:    movk w8, #16618, lsl #16
 ; CHECK-NEXT:    ld1w { z3.d }, p0/z, [x0]
+; CHECK-NEXT:    movk w8, #16618, lsl #16
 ; CHECK-NEXT:    mov w9, #57344 // =0xe000
-; CHECK-NEXT:    mov z6.d, #1023 // =0x3ff
 ; CHECK-NEXT:    movk w9, #17535, lsl #16
 ; CHECK-NEXT:    mov z4.s, w8
 ; CHECK-NEXT:    fmul z4.s, p0/m, z4.s, z3.s
 ; CHECK-NEXT:    mov z5.s, w9
 ; CHECK-NEXT:    fadd z4.s, p0/m, z4.s, z5.s
-; CHECK-NEXT:    mov z5.d, #0 // =0x0
+; CHECK-NEXT:    mov z5.d, #1023 // =0x3ff
 ; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.s
-; CHECK-NEXT:    sxtw z5.d, p0/m, z5.d
-; CHECK-NEXT:    smax z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT:    movprfx z5, z6
-; CHECK-NEXT:    sxtw z5.d, p0/m, z6.d
+; CHECK-NEXT:    smax z4.d, z4.d, #0
 ; CHECK-NEXT:    smin z4.d, p0/m, z4.d, z5.d
 ; CHECK-NEXT:    cmpne p1.d, p0/z, z4.d, #0
 ; CHECK-NEXT:    ld1w { z4.d }, p1/z, [x1]
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6609,6 +6609,13 @@
       }
       return getBuildVector(VT, DL, Ops);
     }
+
+    if (N1.getOpcode() == ISD::SPLAT_VECTOR &&
+        isa<ConstantSDNode>(N1.getOperand(0)))
+      return getNode(
+          ISD::SPLAT_VECTOR, DL, VT,
+          SignExtendInReg(cast<ConstantSDNode>(N1.getOperand(0))->getAPIntValue(),
+                          N1.getOperand(0).getValueType()));
     break;
   }
   case ISD::FP_TO_SINT_SAT:


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