[llvm] 5f94f3b - [RISCV] Refine getMaxPushPopReg like getLibCallID. NFC.
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 7 00:16:46 PDT 2023
Author: Jim Lin
Date: 2023-08-07T15:16:22+08:00
New Revision: 5f94f3b7eac849a172f8029d7992f606db73724b
URL: https://github.com/llvm/llvm-project/commit/5f94f3b7eac849a172f8029d7992f606db73724b
DIFF: https://github.com/llvm/llvm-project/commit/5f94f3b7eac849a172f8029d7992f606db73724b.diff
LOG: [RISCV] Refine getMaxPushPopReg like getLibCallID. NFC.
If save/restore libcall or Zcmp push/pop are enabled, callee-saved registers including ra would be
assigned a negative frame index (-1 for ra, -2 for s0, ..., -13 for s11) by RISCVRegisterInfo::hasReservedSpillSlot.
getLibCallID would find a callee-saved register that has max register id and with assigned negative frame index.
And use this max register to get which save/restore libcall should be selected.
In getMaxPushPopReg (for Zcmp push/pop, similar getLibCallID), it uses extra register class (PGPR) to
check the saved register is in ra, s0-s11 instead of checking the frame index is negative.
This patch just changes the checking for the saved register from `is contained in PGPR` to `has a negative frame index`.
Reviewed By: fakepaper56
Differential Revision: https://reviews.llvm.org/D156393
Added:
Modified:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 79e32306b53b54..da5f18bf7c5e11 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -265,9 +265,10 @@ static Register getMaxPushPopReg(const MachineFunction &MF,
const std::vector<CalleeSavedInfo> &CSI) {
Register MaxPushPopReg = RISCV::NoRegister;
for (auto &CS : CSI) {
- Register Reg = CS.getReg();
- if (RISCV::PGPRRegClass.contains(Reg))
- MaxPushPopReg = std::max(MaxPushPopReg.id(), Reg.id());
+ // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indices to
+ // registers which can be saved by Zcmp Push.
+ if (CS.getFrameIdx() < 0)
+ MaxPushPopReg = std::max(MaxPushPopReg.id(), CS.getReg().id());
}
// if rlist is {rs, s0-s10}, then s11 will also be included
if (MaxPushPopReg == RISCV::X26)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index c3ba4c1e7fdb73..03bdedf637131c 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -132,7 +132,7 @@ const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
}
// Frame indexes representing locations of CSRs which are given a fixed location
-// by save/restore libcalls.
+// by save/restore libcalls or Zcmp Push/Pop.
static const std::pair<unsigned, int> FixedCSRFIMap[] = {
{/*ra*/ RISCV::X1, -1},
{/*s0*/ RISCV::X8, -2},
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 117668072bdc40..505f8d3edc2df2 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -165,15 +165,6 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
-// Registers saveable by PUSH/POP instruction in Zcmp extension
-def PGPR : RegisterClass<"RISCV", [XLenVT], 32, (add
- (sequence "X%u", 8, 9),
- (sequence "X%u", 18, 27),
- X1
- )> {
- let RegInfos = XLenRI;
-}
-
// Floating point registers
let RegAltNameIndices = [ABIRegAltName] in {
def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
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