[PATCH] D156642: libunwind: riscv: disable vector test when __riscv_v not defined

[Alex Bradbury via Phabricator via llvm-commits]

asb requested changes to this revision.
asb added a comment.

Thanks for the patch @xobs - you're right there's a problem here, but I think your current approach needs a slight tweak. `__riscv_v` corresponds to a specific set of the vector extension - you'd be better off checking for `__riscv_zicsr` as you suggest earlier in the thread, or `__riscv_vector`, which is defined if V or any of the Zve* extensions is available (see here <https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#preprocessor-definitions>).

On a sidenote: all the other registers are copied into `Registers_riscv` and then read from there - is it correct that vlenb is read directly through a CSR read on demand?


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